Delay Locked Loop Design

Hi,

I am working on delay locked loop design. My concern is related to loop filter capacitor, does loop capacitor can cause loop stability issue.
please help in this regards.

No. A delay-locked loop has a first-order rolloff, and therefore is intrinsically stable (as long as the loop gain crossover is less than half of the clock frequency). In other words, you can make the capacitor as large as you want; making it smaller risks instability, but only at ridiculously small values (where the capacitor isn't working very well as a filter anyway).

PLL's have a second-order rolloff, and are therefore slightly trickier. DLL's are pretty solid.

Hi Zeker,

while doing corner simulation (slow-slow) and (Fast-Fast) corner i saw that the control voltage (output for Charge pump and loop capacitor) is oscillating(oscillation is around 200mV). so i increase the loop capacitor . and after that it settles down.

so my concern are :
1. Is this is a loop stability issue .
2. why capacitor need to change because its working fine for typical corner case.

please help me in this regards,

Thanks,

1. It could easily be a loop stability issue. Decreasing the capacitor increases the loop gain; too much loop gain with too much delay results in oscillation. The major delay here comes from the sampling nature of the DLL; it exhibits behavior similar to a zero-order hold (ZOH), which is roughly a time delay on the order of the clock frequency.

You can test the DLL's stability by testing its step response to a slight change in the input frequency and observing the capacitor voltage. If the capacitor voltage rings a lot before settling down, then your circuit has poor phase margin. You should increase the capacitor so that any ringing dies down within one or two ringing cycles.

2. Just because your circuit works on a "typical" wafer doesn't mean it'll work right on the atypical wafers; that's why you use corner simulations to begin with. You want your circuit to work on all the wafers that the foundry has determined are within their manufacturing limits. If the foundry starts making wafers near a process corner that your circuit doesn't work on, then you'll be wasting lots of money producing chips that don't work.

Hi All,

can anyone please help me regarding the false locking in delay locked loop.
and how we can avoid this false or anti-harmonic locking.

thanks