hithesh123
Full Member level 6
I am writing a testbench to read a register. For some reason the RD, CS signals are getting update a couple of nanoseconds after the clock. This delay increases as clock cycles increase.
At the first rising edge of the clock, ther is no delay. At the second edge, there is 1ns delay, at 4th there is 2ns etc.
(see simulation waveforms)
At the first rising edge of the clock, ther is no delay. At the second edge, there is 1ns delay, at 4th there is 2ns etc.
(see simulation waveforms)
Code:
----MCU clock----
PROCESS
BEGIN
Clk_Mcu<='0';
WAIT FOR 10.416 NS;
Clk_Mcu<='1';
WAIT FOR 10.416 NS;
END PROCESS;
----- READ/WRITE TO A REGISTER --------
----- 20.833 NS = 48 MHz ------
PROCESS
VARIABLE temp, addr, read_data, write_data : STD_LOGIC_VECTOR(15 DOWNTO 0):= X"0000";
BEGIN
---- READ ----
write_data:=b"0000000000000100";
rd_n<='1'; -- INITIAL VALUES
cs_n<='1'; -- INITIAL VALUES
ale<='0'; -- INITIAL VALUES
WAIT FOR 10.416 NS; -- FIRST HALF BCLK. DON'T DO ANYTHING.
addr:=X"0100"; -- COUNTER GLOBAL CONTROL REG
AD<=addr;
cs_n<='0'; -- MAKE CHIP SEL LOW
ale<='1'; -- MAKE ALE HIGH FOR ONE BCLK CYCLE
WAIT FOR 20.833 NS;
ale<='0';
WAIT FOR 10.416 NS;
AD<=(OTHERS=>'Z'); -- TRISTATE THE AD BUS
WAIT FOR 10.416 NS;
rd_n<='0'; -- MAKE READ LOW FOR 2 CLK CYCLES
WAIT FOR 20.833 NS;
read_data:=AD; -- WAIT FOR 1 BCLK AND READ THE DATA ON THE AD BUS
WAIT FOR 20.833 NS;
rd_n<='1';
cs_n<='1'; -- DE-SELECT CHIP
WAIT FOR 20.833 NS;
WAIT FOR 20.833 NS;
END PROCESS;