Delay in sequential circuits

[muchagracios]

Hey,

I had a query with regard to delay in a Flip Flop.
Does increasing my clock to out delay affect my input to output delay in a D Master-Slave Flip flop?


Thanks,
muchagracios!

 

[Prashanthanilm]

How do you increase CLOCK to OUT delay>?..

The answer is yes. If you are changing the slews of Clock and Data, the output will vary.
If you increase your clock path, then you should be careful about your Set up time.

 

[muchagracios]

Hi Prashanthanilm,

Sorry for the dealyed response, the back ground for my question was scan sticking that is used for testing sequential circuits.
One of the considerations while doing an LSSD or a mux based scan is that if the clock to out delay increases equally everywhere in the circuit, then it has no effect on the input to output delay. I wasn't able to grab this concept as to why there will be no increase in delay in the D to Q path (for a DFF). Even I agree with what you have mentioned.