Delay element in feed forward equalizer (FIR Equalizer)

[circuitking]

Hi All, what should be the delay element in FFE? Is it a flip-flop?
How do we decide whether to use a flip-flop or some other circuit for providing delay in FIR filter equalizer.
Is there any good book on SERDES, FIR filter equalizer design?. Thanks

 

[kaz1]

Hi All, what should be the delay element in FFE? Is it a flip-flop?
How do we decide whether to use a flip-flop or some other circuit for providing delay in FIR filter equalizer.
Is there any good book on SERDES, FIR filter equalizer design?. Thanks

A Filter delay element (Z^-1) is implementable as one register per stage (one clocked flip).
Why do you ask about serdes with FIR?

 

[circuitking]

A Filter delay element (Z^-1) is implementable as one register per stage (one clocked flip).
Why do you ask about serdes with FIR?

To design 3-tap FIR equalizer.

 

[TrickyDicky]

SERDES is a serialiser de-serialiser. It is usally part of a high speed interface. Struggling to see the link with an FIR?

 

[AMS012]

SERDES is a serialiser de-serialiser. It is usally part of a high speed interface. Struggling to see the link with an FIR?

FFE resembles an FIR filter.. and the FFE is used in serdes transmitter output stage for partially compensating for channel loss, and in serdes receiver for equalisation.. so he is asking about FIR in context of serdes.

 

[FvM]

FFE is used both in high speed serial TX and RX. It involves DAC respectively ADC. The FIR bitwidth is chosen according to the analog resolution. Many papers available like e.g. https://www.ieee802.org/3/100GEL/public/18_01/sun_100GEL_01b_0118.pdf