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Delay circuits in clock recovery from Manchester codes

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J

Jing

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I read lots of patents about clock recovery from Manchester codes. They all use delay techniques to delay the Manchester codes by 1/3, or 1/4, or 3/4 bit period. However, they did not mention what is this delay circuits and how to realize them. Could anyone tell me what circuit or element to implement this delay in the clock recovery from Manchester codes? Many thanks
 

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