Delay calculation problem in DC

[yx.yang]

Hi, friends:
I meet a problem when use 90nm memory libraries. The memory have a input port EMA[2:0] to control the output delay of the Q ports. The bigger EMA is, the bigger output delay on Q is. I have read the memory *.lib file, it use the "when EMA == ??" to characterize this feature.
In our RTL design, I have tie EMA to 3'h0.
But when I run DC and let it report_timing. It always use the max Q delay (when EMA == 3'h7) to calculate the timing. So, there will be a big timing violation at this point.
I have checked the DC write gate level netlist, all the memory EMA inputs are tie to "0".
Have you ever occured this problem befre? How do you solve this?
PS: If I use set_case_analysis command to set EMA ports to 0, then DC will use the smallest value to do calculation, then there is no timing violation. As some memories may tie EMA to 0, some may 1, and there are many memories. Can we let DC auto detect the EMA value and choose the right delay value?

Thanks.

 

[dianin]

DC (by default) does not propagate the constant even if the RTL has the logic constant , if you set variable "case_analysis_with_logic_constants" to true , then DC will do constant propagation. Check the setting of that variable .

set_case_analysis is another way to propagate constant in timing analysis.