delay calculation in xilinx

Status
Not open for further replies.
S

shan14

Member level 3
Joined
Aug 18, 2014
Messages
61
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Visit site
Activity points
393
Hi

I have to find the delay in xilinx
when i do synthesis, below values come. are these delay values??


Minimum input arrival time before clock: 6.394ns
Maximum output required time after clock: 6.492ns

for total delay do I have to add these two values??
 

Hi

Delay means , For a particular vhdl code, I have to find the delay of the circuit.

Minimum input arrival time before clock: 6.394ns
Maximum output required time after clock: 6.492ns

so , are these above values are delay values of that circuit or not????
 

If you mean the delay through the entire circuit (assuming combinatorial circuit), then no - those values are nothing to do with that - they are delay at the IO pads.

You cannot calculate the delay through the entire circuit because it varies with PVT (process, voltage, temperature).
1. Process - Each time you compile the code the fitter will place the design in different parts of the chip, affecting the routing delays
2. Temperature - as it gets hotter, the delay changes
3. Voltage - different voltage = different delay

On the other hand, if you have a completly synchronous circuit, the latency is easy to calculate from the number of registers there are in the longest path. THen you just take (N * clock frequency)
 
Reactions: shan14

    S

    shan14

    Points: 2
    Helpful Answer Positive Rating
TrickyDicky said:
1. Process - Each time you compile the code the fitter will place the design in different parts of the chip, affecting the routing delays
Click to expand...
This is incorrect. Process variations have absolutely nothing to do with the fitter or the routing. Process variation comes from transistor delay differences due to physical differences between die. Differences in parasitics, channel dimensions, doping, etc.

So FPGA timing is made up of PVT variations along with placement and routing.
 
Reactions: shan14

    S

    shan14

    Points: 2
    Helpful Answer Positive Rating
I think shan14 wants the delay through the circuit. If that is the case just simulate the design and note down the number of clock cycles from input to output. This should give you the delay.
 
Reactions: shan14

    S

    shan14

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…