delat Vbe/Temp = -2mv really ??

[andy2000a]

vbe temperature coefficient

q1 many text book said bandgap design use Vbe + delta_VT
and get zero TC(temp coffefficient )
and said delta_Vbe/ temp = -2mv , delta_Vt/ temp = + 0.085mv

really ?? in CMOS 0.5um / 0.35um /0.25um /0.18um
have the same value or not ??

q2: we usually use " B S song CMOS bandgap " but we only use pnp is 1:N:1
not 1:N:N -> see PR gray analysis & design of analog IC
Fig 4.50

if we use Fig4.50 pnp => 1:N:N
Vbg = vbe + K * Vt *ln(N)

but if we use pnp = 1:N:1
Vbg = vbe + K * Vt *ln(N) or not ?

Q3. many designer use N=8 or 23 or 49 which is better for zero TC

 

[devrimaksin]

delta vbe

Vt TC slope is easy to calculate:
Vt=kT/q => dVt/dT=k/q
so it is not process dependent, it is constant.
Vbe TC is not exactly -2mV/C, but it is close
to that number you can run a quick simulation
to find out the actual slope for a given technology (but it is generally higher than -1.8mV/C).

The Value of N is not important in terms of design.
After all what you are trying to achive is dVbe/dT-dVt/dt=0. So what is important is K.ln value so that it makes the TC is zero. For layout purpose though, it is advantageous to chose N equal to 8, because the matching between Q1 and Q2 is important for the performance, notice that the collector and base terminals of Q1 and Q2 are the
same, i.e. gnd. So in layout you can lay down the emitter areas by 3x3 and use the incircling 8 emitter
area as Q2 and one single island at the center as Q1's emitter area. So Choosing 8 is advantageous in terms of layout (hence matching). Notice that
actually, in the schematic you have to match Q2 and Q3 also so you have 2n+1 base area. So you have to think about this, you can use a 3x3 (4 4 1) matrix or 5x5 (12 12 1) or 7x7 (24 24 1)

 

[cetc1525]

temperature co efficient of vbe

delta Vbe is probably =2,but it depends on the fab. we test it was 2.2or even larger.

 

[JPR]

vbe vs temperature

As to your question about 1:n:n vs 1:n:1. They will BOTH work. There are some differences between them, but, relating only to making the tempco zero, you only need to consider that the difference in voltage between them will be Vt*ln(N), and you can easily adjust for this by changing K.

If you define Vben as vbe with n devices, Vbe1 as vbe with 1 device, and K as the multiplication factor that is needed for zero tempco (using n devices on the output leg), Vbgn being the output with n devices and Vbg1 being the output with 1 device:

Vbe1 = Vben + Vt*ln

Vbgn = Vben + K*Vt*ln
Vbg1 = Vbe1 + (K-1)*ln

 

[Question]

bjt vt tempco

you'd better simulate the circuit to get the temp performance. The calculation is only a base.

In Razavi's book (P392), it is 'the size of Q3 are somewhat arbitary so long as the sum of the two terms gives a zero TC'. So, both of 1:N:N and 1:N:1 are Ok. The first N is inportant. I think the second N is for matching.

 

[electronrancher]

vbe and temperature relationship

delta Vbe is probably =2,but it depends on the fab. we test it was 2.2or even larger.

interesting - can you post these measurements? i am surprised

 

[Fom]

temperature coefficient delta vbe

It is not only kT/q. IS also have temperature coefficient - XTI. For fixed foundry Vbe temperature coefficient depends on junction current density also.

 

[ysz]

vbe versus temp

It is not only kT/q. IS also have temperature coefficient - XTI. For fixed foundry Vbe temperature coefficient depends on junction current density also.

Hi, Fom
Could you tell me more details about XTI?

 

[Fom]

delta vbe temperature coefficient

See Martin&Johns Analog Integrated Circuits Design page 354 and any reference with BJT spice model equations. In expression (8.10) m corresponds to xti parameter in spice model.