Default type of a Systemverilog port

Hello,

Suppose we have an output module port named: x.
We want x to be defined as type "logic".

Do we have to explicitly define it:

Or is it enough to define it as:

Is x considered to be of "logic" type by default ?

IIRC, it is wire. verilog has `default_nettype <type>. IIRC the default is "wire". you can get `default_nettype logic, at least I think. In 2020, I think it is more common to see `default_nettype none, which forces all regs/wires/logics/etc... to be declared.

`default_nettype none

Click to expand...

Where is this line of code set ?

A port has a direction, kind, range, datatype, and a name. Everything except the name is optional. SystemVerilog has an elaborate set of implicit defaults for the first port, and subsequent ports. They are somewhat convoluted so SystemVerilog extensors remain 100% backward compatible with Verilog.

If you omit both the kind and datatype, the default kind is wire and default datatype is logic. If you specify the kind, but omit just the datatype, the default datatype is also logic. These rules work for both input and output ports. The following 3 statements are equivalent (same for input ports)

There is a difference between input and output ports when you have an explicit datatype but no kind. For input ports, the default kind is wire, but for output ports, the default kind is var (variable).

So your first code example is declaring a variable output port, and your second code example is declaring a wire(net) output port.

This is explained further in section 23.2.2.3 Rules for determining port kind, data type, and direction of the IEEE 1800-2017 SystemVerilog LRM.