Deep Reinforcement Learning for automated analog IC design sizing- Suggest me my path is right or wrong?

Dear Mentors, I'm a newbie in this research community, and I planned to do my research in the analog ic design sizing (front end) using optimization techniques, especially deep reinforcement learning. I need all your suggestions, whether my identified research gap can have much space to explore or you can suggest any right way to progress my research. Thanks in advance for all your suggestions. Your little information means a lot for me.

 

[dick_freebird]

I have to say that (as an analog IC designer) this has little
evident utility to me - the task can be simply handled by
some nested parameter loops and a quick glance at some
affected parameters' "happy place". It's what I've done for
a long time and represents a trivial slice of the design effort.

Now as a demonstration that you had learned something
of AI / ML, maybe there's traction for other reasons (like a
"suggestion" from your professor who's got a paper of her
own to write).

If it were able to "think" of all the topologies and
contstraints in pursuit of a truly general and yet spec
compliant (in multiple dimensions) outcome, that might be
a "point tool" of some utility to someone. But if all it does
is convince a CAD director that a new grad can do my job
for the low low cost of an annual license fee... don't be
that guy.

 

[nitishn5]

There are some specific niches in analog design where the number of circuit topologies are few and the main task is the optimization of transistor sizes and layout parasitics. Something like high speed drivers and such.
A solution using optimization techniques "might" be useful in those scenarios.

The main limitation is that sizing of transistors is usually a very small part of the design problem. We still have to layout those transistor, check if that changed anything. Then maybe redo the layout if it does not meet the spec.
Also, connect the transistors to all the other things on the chip and see the effects of all that. So I am not sure how much this would help in the long run.

PS. The above observation/opinion comes from place of ignorance of the potential AI/ML. For all I know, your method could "think" and make decisions like @dick_freebird said.

 

[p_sridhar]

There are some specific niches in analog design where the number of circuit topologies are few and the main task is the optimization of transistor sizes and layout parasitics. Something like high speed drivers and such.
A solution using optimization techniques "might" be useful in those scenarios.

The main limitation is that sizing of transistors is usually a very small part of the design problem. We still have to layout those transistor, check if that changed anything. Then maybe redo the layout if it does not meet the spec.
Also, connect the transistors to all the other things on the chip and see the effects of all that. So I am not sure how much this would help in the long run.

PS. The above observation/opinion comes from place of ignorance of the potential AI/ML. For all I know, your method could "think" and make decisions like @dick_freebird said.

Thanks for your valuable suggestions. Unfortunately, I'm supposed to continue my research in that area without any compromise with my supervisors. In this scenario, can you give me any directions? How can I move further?

 

[dick_freebird]

In that case you shut up and march.

But you might take a moment and reflect on what you want out of the exercise. Because it seems that you are in a moment that may let you bend the direction, if not the pack or the pace.

For one example, the chore of stabilizing an amplifier has always been more difficult than arriving at a reasonable place on the front end devices' gm curve, for me. There are poles and zeroes to move around and to keep stable over application corners.
There are topology choices to mix-n-match. There are secondary concerns that bear on topology suitability, like how a Miller comp is efficient at stabilizing gain/phase but hurts HF PSRR in a PMOS LDO (and the one-legged output presents its own challenges with wide load and input supply ranges).

Look to the "rough spots in the design flow" if you intend this activity to shine on your resume. Pick an easy win if it's a topic that you don't want to make a career of.


Cut-and-try is how I go at it, and that human-in-the-inner-loop work style is ripe for automation / assistive tools.

 

[nitishn5]

Like @dick_freebird also suggested, I would also suggest that you look into the Frequency Compensation of Low Speed Amplifiers.
For example, Take an LDO with some specifications such as load settling, line settling, psrr, bandwidth, phase margin etc. Put a bunch of compensation capacitors and then run your AI/ML algorithm on it to set the sizes of the different devices.

PS I say low speed, so that you are not limited by layout.
PPS The above description is more like a linear optimization problem. But that just stems just my ignorance of AI/ML.