Decoupling placement in pcb

[ashokgak]

Hi,
I am working as a PCB designer.I have one doubt in placement of decoupling capacitor in PCB.
For one power pin in the circuit,they are used 4 different values of capacitor like 10uf(1),1uf(2),0.1uf(1).Which capacitor i can place near to power pin... Please help me with your answer.

Thanks in advance
Ashok

 

[srizbf]

the one with the lowest value(0.1uf here)

 

[ashokgak]

May i know the reason for low value., Please..

 

[srizbf]

the ceramic in your example decouples the ic generated supply noise to ground.

 

[ashokgak]

Thanks....

 

[marce]

Look up and learn about decoupling capacitors and the frequencies they qwork at, and how inductance can affect them, they are critical to PCB design...
Start at the AVX site...
The lowest value in the smallest case provide the highest frequency decoupling and helps limit the voltage droop during switching by providing power, the next sizes then refill this capacitor like a bucket brigade.
The 10u and 1u are reservoir caps, as they wont do much high speed decoupling.

 

[tsvetelin_velkov]

Knowing more about the circuit will definitely help other to give better suggestions, why not you place that part of your schematic here, or just say what is the chip that you want to decouple ( power decoupling is not always strait forward, it depends on your goals ). Usually the smallest value cap is placed on the pin, then next to it are the larger ... as big is the decoupling cap as far you can place it, as close you place your caps as good they will do the decoupling job, and don't forget to provide a good low inductance path to ground, i.e. ground plane or thick tracks.

I have doubts about 10u and 1u, does someone think that having both will make sense? Usually you put one big cap at the output of the regulator - let's say 100u, than one smaller at the block that is supplied - let's say 10u, then one ceramic cap at the Vdd pin of your chip - let's say 100n, but could be also 10n or even 1n ( could be combined with uF range cap as well ). Values given here depend on application and circuit, I give them only as example!

Also, try to use caps with low ESR. Tantalum caps are good, as they have lower ESR - they are able to keep their function to higher frequencies.

 

[marce]

Got to disagree slightly, power supply decoupling has set goals that must be achived to fulfill the elctrical performance of a PCB layout, that is clean noise free power that stayes withing theb requirements of the circuit, no droop, and minimise ground bounce.
I would suggest a good look around at the information regarding de-coupling or bypass capacitors it is one of the most widly documented aspects of PCB design.

 

[tsvetelin_velkov]

Got to disagree slightly, power supply decoupling has set goals that must be achived to fulfill the elctrical performance of a PCB layout, that is clean noise free power that stayes withing theb requirements of the circuit, no droop, and minimise ground bounce.
I would suggest a good look around at the information regarding de-coupling or bypass capacitors it is one of the most widly documented aspects of PCB design.

I fully agree. However there are tricky points, like decoupling of big high frequency digital chips, or small digital but very high frequency chips. Also having two caps with different values - like 220n and 10n as decoupling may create a loop and area in frequency domain where you have a drop in performance, your resistance will increase like having a hill shape in certain frequency range. If you are lucky that your chip signals are in this valley, then it might have problems - power supply drop, unstable operation / reset of digital core, even oscillations. That is why I say - decoupling is not always strait forward.

For really high frequency decoupling I recommend COG caps. They have only small values, a few nF, but this is enough for very high frequency decoupling.

 

[awaw]

For one power pin...

This pin is a special pin like power for analog PLL or somewhat other senitive thing, right?
In this case you often can simplify your life by deleting some unneeded capacitors.
Often these caps are installed only because of datasheet typycal recommendations and without any calculations.
Try to communicate with schematic creator and ask about real need of these caps.
Without a inductive serial element like ferrite bead the effectiveness of caps is very reduced because they are not isolated of main plane and must filter any noise that comes from all other board elements.
So you should verify the existence of such ferrite bead and overall response of a filter that is formed by bead and capacitors.
If you see that filter response is sufficient to damp noise in your given design with for example only two caps then you can delete other unneded caps and simplify the layout.

 

[marce]

Hi Tsvetelin,
I agree that de-coupling is not straight forward, but I also think that due to its importance in PCB design, that PCB designers should learn as much about the subject, and especialy component placement for optimum decoupling.
I agree on the use of COG for high frequency and critical circuitry, we use COG for all crystal Osc. decoupling.

For all
Here is a link to the AVX technical papers, another good source is FPGA, Microprocessor etc application notes, where PLL's are discused in detail. Generaly most devices will cover the basic aspects of decoupling in the data sheet, usualy with a more in depth guide to optimum layout for the device, these are all worth reading.
- Technical Articles AVX Online

Some notes on the addition of ferrites:
**broken link removed**
**broken link removed**

 

[marce]

more reading and an interesting take on de-coupling...
**broken link removed**