Decoupling caps routing

[sapphire_2010]

hi all,
I need to know what is the standard method for placing and routing decoupling cap. Attached is the picture
(1) VCC pin of IC is first routed to SMT pin of decoupling cap then to via
(2) VCC pin of IC is routed to via (common) of decoupling capacitror
(3) VCC pin of IC is routed to an individual via and decoupling has also an individual via
Please specify which one is correct and why?

thanks & regards
SA

 

[senilicus]

Have a look at this article. **broken link removed**, Designing with decoupling capacitors.

 

[marce]

No 3 with power planes, has the lowest inductance. Even better if vias stubs come from other edge of cap pads.

 

[ramu3584]

I think No1 is correct because the power entering through the capacitor.

 

[marce]

Nope, its all down to inductances, you are trying to minimise the loop area and any stray inductance, the gnd connection is part of the loop.
Have a read of this lot and you'll start to get the basic idea.
Note that layer stack up and power plane positions will also have to be quantified.
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https://www.emcs.org/acstrial/newsletters/spring09/designtips.pdf
https://cache.freescale.com/files/32bit/doc/app_note/AN2747.pdf
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PCBDESIGN007 Quiet Power: Inductance of Bypass Capacitors, Part II
https://www.x2y.com/publications/decoupling/jul24-06.pdf

 

[loosemoose]

there is no one correct solution. you need to let us know first what you are trying to prevent.
keep noise from getting to the power pin? ground bounce is a problem? high speed application ? maybe audio application?
sensitive analog circuit?

btw, you could also place the cap on the right hand side of the chip between the power and ground pin. Or as to prevent ground bounce you would place it closest to the ground pin.

 

[marce]

No there is a correct solution regarding routing of de-coupliung capacitors and that is number 3, read up!
Please read up all there is on decoupling capacitors and how they work. It is inductance that is the problem, so creating the LOWEST inductance path makes the cap more effective.
Placing next to the ground pin does not make it any better for ground bounce (that is a myth), it is the total LOOP area that matters, the best placement is preferably equidistance between the pins you are de-coupling. It also depends on where the power planes are in the stack on whether it is better to place the capacitors on the same or opposite side of the board, whatever gives the LOWEST inductance.
To quote Henry Ott, "we are placing an L-C network between the power and ground, not a capacitor", thus it is a series resonant circuit, and as such once it passes any noise is above the circuits resonant point, inductance becomes the dominating factor and it doesn't work as a de-coupling capacitor. Looking at the systems requirements and engineering a solution is much better than random sprinkling of capacitors, and in a lot of cases (most!!) that is what happens, then you end up trying to treat the symtems (noise) and generaly end up adding to your woes.
For a bit of extra reading the problems and benefits of adding ferrite beads to the PDS equation.
You also need to choose a capacitor with the right parameters for decoupling, for the higher frequencies a low ESL is desirable, that means small package and inherant low parasitic ESL, also ESR is important, but not to low!
Howard Johnson - High Speed Digital Design, page 271 onwards.
Henry Ott - Electro Magnetic Compatability Engineering, page 431
Lee W Ritchey - Right the First Time, Chapter 34
Sorry if I seem to be getting a bit wound up, but decoupling capacitors are a bit of a hobby and years of having to work (even in this day and age) with EE's with their own myths regarding decoupling is a pain. Some engineers throw decouplers on a board like they were confetti, some use packages that are to big for the capacitor value and frequency's that are of interest etc etc. Start adding ferrite beads into the equation and your PDS (power delivery system) is goin to be noisy.

 

[loosemoose]

hi marce

all the papers you refer to are digital high speed application?

 

[marce]

The rules are the same for any frequency of circuit operation, not only are you decoupling the power supply (ie supplying the instantaneous current requirement) but you are also bypassing any high frequency noise, such as rf interference for audio, thus the rules are the same. Texas have some excellent app notes related to their Burr Brown op amps, but for once I cant find the info (I have 33MB of PDFs on decoupling!).
The fact that adding a decoupler is adding a resonant network, and low value capacitors only work at certain frequencies, thus a 0,.1 cap will work at the same frequency whether its a high speed digital board (any board with Rt of 1ns or less as well) or an analogue board.
Where things would vary is when using reservoir capacitos, but we'll save that for a later day.
Just for you follow this link and half way down are some extra links to PlanetAnalogue notes on choosing decoupling capacitors.
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