Decoder with 32 bus width

[Steve Eric]

Hello Guys, I'm new in encoder and I'm not really understand the question below. Could someone please help me? Thanks!

Consider a memory bank consisting 32,768 bytes of registers. The bus width in use with the older generation computer was 32. How would you design a decoder such that all 32,768 bytes can be addressed separately?

My idea is that I merely need 15 bus address to cover the 32,768 data.
2^15 = 32,768. Is my idea correct?

 

[FvM]

That's right for byte addressable memory (32kx8). If the memory organisation is 8kx32, you need 13 address lines and possibly 4 byte write enable lines.

 

[barry]

Not quite sure of the intent here, but I THINK the question is a little more complex. Since the "older" computer bus was 32 bits (I'm assuming that means the data bus), that means that 4 bytes at a time were accessed (4x8=32). Thus, you'll need 13 bits to access each 32-bit word, and then you'll need 2 bits to access 1-of-4 bytes of each word. That's still 15 bits, but the arrangement is a little different.

 

[FvM]

To support byte, word and doubleword writes, a 32-bit data bus has usually byte enable lines instead of a 1-of-4 selection. Reads are performed 32-bit wide.

 

[Steve Eric]

Hi, Thanks for your reply. I'm sorry that I still not get the ideal on how to design the decoder. Could you explain more detail? I'm sorry for any inconvenient.

 

[FvM]

To design a decoder, you need to know which control signals are used by the "memory bank" and the 32-bit bus. If it's not specified in the homework problem, you need to assume something from the lecture stuff.