decoder verilog code

[vead]

hello,
I wrote code for decoder but when I compiled code I got error

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Code Verilog - [expand]
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module decoder (clk,rst,opcode,ram_sel,rom_sel,alu_sel,pc_sel,acc_sel,ext_rom_sel,ext_ram_sel,register_sel);
 
input  clk ;        // clock 
input  rst;         // reset 
input opcode  ;
output ram_sel [7:0];     // select ram for read and write 
output rom_sel [7:0];   // select rom for read 
output alu_sel [7:0];   // select alu  
output pc_sel  [7:0];   // select pc 
output acc_sel [7:0];     //select accumulator  
output register_sel [7:0]; //select register 
output ext_rom_sel[7:0];  //select rom for read 
output ext_ram_sel[7:0];   // select ram for read and write 
 
reg [7:0] ram_sel;
reg [7:0] rom_sel;
reg [7:0]alu_sel;
reg [7:0] pc_sel;
reg [7:0] acc_sel;
reg  [7:0] ext_rom_sel;
reg [7:0] ext_ram_sel;
reg  register_sel [7:0];
always @(rst)
begin 
case (rst)
00000000:ram_sel =00000001 ;
00000000:rom_sel =00000010 ;
00000000:alu_sel =00000100 ;
00000000:pc_sel  =00001000;
00000000:acc_sel =00010000 ;      
00000000:register_sel =00100000 ;
00000000:ext_rom_sel =01000000; 
00000000:ext_ram_sel =10000000;
endcase 
end 
endmodule

---

error

Error (10773): Verilog HDL error at decoder.v(11): declaring module ports or function arguments with unpacked array types requires SystemVerilog extensions
Error (10048): Verilog HDL error at decoder.v(31): values cannot be assigned directly to all or part of array "register_sel" - assignments must be made to individual elements only
Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 14 warnings
Error: Quartus II Full Compilation was unsuccessful. 4 errors, 14 warnings

note: I did not see any option for code table so I have pasted directly

 

[mrflibble]

Please edit your post and use

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Code Verilog - [expand]
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tags for your code. Also please use 4 spaces for indentation (right now you have no indentation at all). Main reason for this: it will give us easy to read line numbers that should hopefully match up with the line numbers in your errors. And then you have your solution faster. Thanks. :)
 
[b]Edit:[/b] And please make sure you post the full code of that file, not just part of it. Otherwise line numbers from your error messages still might not match...

---

 

[ANS HAFEEZ]

I just make a little change and it is compiled
try it

module decoder(clk,rst,opcode,
ram_sel,rom_sel,alu_sel,pc_sel,
acc_sel,ext_rom_sel,ext_ram_sel,
register_sel);
   input clk ; // clock 
   input rst; // reset 
   input opcode ;
   output ram_sel [7:0]; // select ram for read and write 
   output rom_sel [7:0]; // select rom for read 
   output alu_sel [7:0]; // select alu 
   output pc_sel [7:0]; // select pc 
   output acc_sel [7:0]; //select accumulator 
   output register_sel [7:0]; //select register 
   output ext_rom_sel[7:0]; //select rom for read 
   output ext_ram_sel[7:0]; // select ram for read and write 

   reg [7:0] ram_sel;
   reg [7:0] rom_sel;
   reg [7:0]alu_sel;
   reg [7:0] pc_sel;
   reg [7:0] acc_sel;
   reg [7:0] ext_rom_sel;
   reg [7:0] ext_ram_sel;
   reg [7:0] register_sel ;
   always @(rst)
      begin 
         case (rst)
         00000000:ram_sel =00000001 ;
         00000000:rom_sel =00000010 ;
         00000000:alu_sel =00000100 ;
         00000000:pc_sel =00001000;
         00000000:acc_sel =00010000 ; 
         00000000:register_sel =00100000 ;
         00000000:ext_rom_sel =01000000; 
         00000000:ext_ram_sel =10000000;
         endcase 
      end 
endmodule

 

[ads-ee]

Clean_formatting & Syntax_tags == forum_help

You've been asked previously to minimally do that much to your posted code. I will help when the minimum has been done.

- - - Updated - - -

I just make a little change and it is compiled
try it

Fixing a compilation error isn't the main problem. The OP's code doesn't even do what they want, besides being poorly written.

 

[rberek]

A hint:

reg [7:0] ram_sel;

and

reg ram_sel [7:0];

are NOT the same..

The first is a packed array, while the second is an unpacked array. A packed array can be considered a group of signals, so you may assign a value to each of the bits with a single assign statement. That is not true for an unpacked array.

You have mixed unpacked and packed assignments to your signals, which you should not do.

That is exacerbated by your insistence on using very old coding styles.

Among other things.

r.b.

 

[ads-ee]

A hint:
...
are NOT the same..

The first is a packed array, while the second is an unpacked array. A packed array can be considered a group of signals, so you may assign a value to each of the bits with a single assign statement. That is not true for an unpacked array.

You have mixed unpacked and packed assignments to your signals, which you should not do.

That is exacerbated by your insistence on using very old coding styles.

Among other things.

r.b.

Until vead starts doing at least the minimum of adding tags to his posted code (which is part of the forum's rules) and shows us some modicum of respect by taking our coding style suggestions and using them so we can easily read their code (see: https://www.edaboard.com/threads/323557/) I would refrain from even giving hints. Looking back on their previous post, I suspect they will disregard anything suggested (especially anything that will make it easier for forum members to help). I'll admit they've marginally improved their coding style, at least have some white space in their code: reg [7:0] rom_sel; instead of reg[7:0]rom_sel;

 

[rberek]

Fair enough!

r.b.

 

[ads-ee]

I feel that if a member has 137 posts (vead's current total) by now they should know the forum rules and should have taken advice from members with lots of Helped: #/# points.

I'll try to give slack to a new member with <10 posts, but 137? No way!

 

[vead]

first I am really sorry, I am feeling nerves actually, I want to ask in my previous post, but I did not ask . I didn't understand actually what you told me in my previous post
I am learning by doing myself. I saw some sample code on google and then I started to write some code . you all told me suggestion about coding style.I want to learn coding style that you want. Its batter for me if someone will give me sample code. actually I don't understand where did I am wrong so please give me sample I will see that code style and I will write that type of code

please don't understand me that type of guy who does not follow forum rule

 

[rberek]

Vead

I assume you are not a bad person but you are a very frustrating person to try to help.

In your last thread, Procedural Assignment error (verilog), the first reply you got was from Dave Rich, who works in the EDA industry and has forgotten more about HDLs than I will ever know, He told you to use Verilog-2001 port syntax. I typed an example of that syntax in post #10. Yet you kept using the old syntax for the subsequent posts, in spite of telling people you had downloaded a PDF explaining the new port syntax. At that point, people gave up in frustration because you weren't acting on any advice.

Then, in this post, you came back with new code where you still did not listen to advice and you used the old port syntax. Worse, your first errors were caused by your use of the old syntax and your inexperience.

As well, you seem to have regressed in other ways. Your other posts had case statements that at least made sense, but this one has one that makes no sense. You have a case statement with 8 identical 8-bit case indexes, in spite of the fact that the case operand is a single bit and identical indexes are incorrect..

Because you keep making the same mistakes despite people telling you otherwise, the helpers eventually give up and move on, as it appears has happened to some degree here.


The people helping here are professionals in the industry, educators, advanced students and skilled hobbyists. They are helping you in their spare time, often while their paid work is simulating or compiling. No one has time to teach someone from scratch. They don't have the time to take you from zero to hero in digital design or to spend 30 posts persuading you to see their point. After a few tries, people go help other people who are wiling take advice. ( Not that you should believe everything you read on the interwebs though. Some of the advice here, including possibly my own, is sometimes shite).

So, the words of advice to newbies that are oft repeated but always useful:

1) If you don't understand digital design, and specifically, the digital design you are trying to create, don't bother writing RTL. You can't describe what you don't understand.

2) Write an HDL file like a hardware description, not like a procedural software program.

3) If you are going to teach yourself HDL coding using random scraps of code you find on the internet, prepare yourself for trouble; there is plenty of garbage code out there. If you must train yourself this way, also have on hand a good textbook or tutorials, so that you can understand what the designer is trying to do, and so that you also understand what each HDL construct is used for and what its proper syntax is.


I suggest that in the next post you make, you use Verilog syntax tags, as requested, and that you write a module with modern port syntax. And take some time to proofread your code, so that obvious syntax errors are corrected.

Don't beat yourself up over this, but do try to help everyone help you!

r.b.