Declaring an unconstraind varaible inside a function

shaiko said:

In VHDL 2008
Is it possible to declare an unconsrained unsigned variable in a function?

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shaiko said:

For example:

Code:

function some_function ( x : unsigned ; y : unsigned ) return unsigned is
variable result : unsigned ; -- "result" is defined as an unconstrained unsigned.  [COLOR="#FF0000"]KJ:  If left as unconstrained, then how would you expect it to eventually get the size defined?[/COLOR]
begin
if x > y then
result := x ; -- "result" gets constrained according to the size of x  [COLOR="#FF0000"]KJ:  No it does not.  What happens is that VHDL checks to see that 'result' and 'x' are both of the same type and the same size.  If they are not compatible an error is declared when compiling.[/COLOR]
else 
result := y ; -- "result" gets constrained according to the size of y  [COLOR="#FF0000"]KJ:  Ditto[/COLOR]
end if ;
return result ;
end function some_function ;

Click to expand...

function some_function ( x : unsigned ; y : unsigned ) return unsigned is
begin
if x > y then
    return x ;
else 
    return y ;
end if ;
end function some_function ;

function sel(Cond: Boolean; If_True: integer; If_False: integer) return integer is
begin
   if Cond then
      return If_True;
   else
      return If_False;
   end if;
end function sel;

function some_function ( x : unsigned ; y : unsigned ) return unsigned is
variable result : unsigned(sel(x>y, x'high, y'high) downto sel(x>y, x'low, y'low));