decimation in design Flash adc

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pansoo kim

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I have knew that we use decimation circuit for ease measurment in design Flash ADC.
And I had simulate Flash ADC using decimation circuit.

Then ideal dac output wave, none using decimation circuit was well reconstructed.

On the contrary, at using decimation circuit the adc output binary code was decimatied correctly but reconstructed ideal dac wave was not similar input wave.

There are too many errors.

Please let me know what I know wrong.
 

It seems that the decimation circuit is not right. The output has aliasing.
Maybe add a filter before decimation circuit
 

I think decimation circuit behave correctly.
 

When using decimation your reconstructed waveform should not change in every clock cycle, as it seems to be the case. For example if you decimate by 4, it should only change once in every 4 clock cycles. You have something is wrong there....
 

you should upload your schemtic and check where are the errors!
 

I think this pdf doc will help u to get the decimated reconstruction DAC
 

the decimation may be have the same function as the delta-sigma adc.
 

Thank you for your answers.

I understood and solve the problem.

There are some very important and basic misunderstanding.

I understood now that decimation in flash adc is not decimate the binary output but decimate clk and sample the binary output using decimated clk.

Is it ok? ^^
 

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