[SOLVED] decimal numbers in vhdl

When using std_logic_vectors(xx down to yy) I can use either binary numbers
in the form "11010101" or hex numbers in the form x"00".
How can I use
decimal numbers?

I guess you can use real datatype.
SIGNAL A: real := 0.0; -- double

ravics said:

I guess you can use real datatype.
SIGNAL A: real := 0.0; -- double

Click to expand...

tnx
but i dont want use real type or integer
i wana use std_logic_vector

what about the function , conv_std_logic_vector?

sometimes you can use as --*****************************



entity decimal is
Port ( clk : in STD_LOGIC;
res : in STD_LOGIC;
cnt : out STD_LOGIC_vector(0 to 5));
end decimal;

architecture Behavioral of decimal is

signal cnt_s : std_logic_vector(0 to 5);

begin

SM : process (Clk)
begin
if (Clk'event and Clk = '1') then
if (Res = '1') then
cnt_s <= "000000";
elsif cnt_s = 16 then --*****************************
cnt_s <= "000000";
else
cnt_s <= cnt_s + 4; --*****************************

end if;
end if;
end process SM;


cnt <= cnt_s;

end Behavioral;

well in define of
constant constant8: std_logic_vector(15 downto 0) := 20000;
the vhdl take error.:sad:
what should i do????

You have to remember that a std_logic_vector is not a number, or integer, or signed, or real or any other type of number. It is just a collection of bits. So actually you are not assigning it with a binary number, or hex, it is a string ("00101001", x"FFAA", o"1745" etc..).

If you want to assign integers, you need to convert an integer from the integer type to a std_logic_vector. but there is one main problem with treating a std_logic_vector as an integer: Is it signed or unsigned?

To get round this, there is the package called numeric_std (an IEEE standard) that defines a signed and unsigned type that are very similarly to std_logic_vector but there are functions to treat them as integers.

Before you get started - I really really really recommend you stop using std_logic_unsigned, std_logic_signed or std_logic_arith. They are non-standard libraries. Numeric_std is the real standard, and if you start using more advanced libraries (like the fixed point libraries) they are incompatible. So stick with numeric_std. because conv_std_logic_vector is part of this non-standard library, you should NOT use it.

Because numeric_std defines signed and unsigned types, there is no need to use a std_logic_vector if what you want is an unsigned. There is also nothing wrong with using an integer. If you want an integer, use an integer.

signal a : integer range 0 to 1023 --limit to 10 bits

a <= 10;

then, if you really really have to convert it to a std_logic_vector

slv <= std_logic_vector( to_unsigned( a, 10) );

but like I said, there is nothing wrong with using integers, unsigned, boolean or any other type on a port definition, just make sure you stick with array types (including signed and unsigned) at the top level.

Here is an example that will work and synthesise perfectly fine:



---------- Post added at 11:37 ---------- Previous post was at 11:36 ----------

maia31 said:

well in define of
constant constant8: std_logic_vector(15 downto 0) := 20000;
the vhdl take error.:sad:
what should i do????

Click to expand...

constant constant8: std_logic_vector(15 downto 0) := std_logic_vector( to_unsigned(20000, 16) );

signal a : integer range 0 to 1023 --limit to 10 bits

signal a : integer range 1024 to 2047 --in some situations limit to 10 bits

I hate Integer

treqer said:

signal a : integer range 0 to 1023 --limit to 10 bits

signal a : integer range 1024 to 2047 --in some situations limit to 10 bits

I hate Integer

Click to expand...

With correct design practice, you dont need to limit the range. If you connect the integer to a top level vector type, the synthesisor will trim the unused bits.

I do not use Integer if you want to then convert it into a bit signal, and work with individual bits.

treqer said:

I do not use Integer if you want to then convert it into a bit signal, and work with individual bits.

Click to expand...

yah
in the end i decide use the binary form of my number
but it is unusual that vhdl
dont have s.th for decimal
c# has

-------------------and tnx every one for their help

I think you're getting very confused.
Like I said, an integer is not a bit type. VHDL is strongly typed so has some strong rules, hence why you cannot assign an integer directly to a std_logic_vector.

Also comparing VHDL to C# is not valid, as VHDL is not a programming language.