Decimal number concantenation using Verilog at output

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Antares.

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Hi, I'm working on a verilog code wherein i have to concantenate the results of two operations. Like, the result of first operation is 6 stored in temp1 and the second operation is 25 stored in temp2. I want to concantenate these two to get 625, but when i synthesize the code the numbers are internally processed in hex and concantenated output {temp1,temp2} is not 625....please help me.

Here is the code, its supposed to perform multiplication using Vedic math algorithm. the results of temp1 and temp2 are the LHS and RHS of the final product, so i've to concantenate those two.
Code Verilog - [expand]
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module M1(a,b,p);
input [15:0] a, b;
output [31:0] p;
    
reg [31:0] p;
reg [15:0] temp1, temp2;
     
always @ (a or b)
begin
 
temp1 = (a - 1);
temp2 = (b - temp1);
 
p <= {temp1|temp2};
end
endmodule
 
Last edited by a moderator:

Internal number representation isn't hex or decimal, just binary. You should figure out what you mean with "concatenate". I guess you mean the operation c = a + 100*b
 
FvM is right, you are trying to concatenate in binary and see the result in base 10. What you are really doing is, considering 3'd6 and 5'd25

6*2^5 + 25 = 6*32 + 25 = 217
 

I have inserted the code. That may give more details.

It is supposed to perform multiplication operation using Vedic math algorithm. The results stored in temp1 and temp 2 form the LHS and RHS of the final product. Thats y i wanted to concantenate them.

Code Verilog - [expand]
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module M1 (a,b,p);
input [15:0] a, b;
output [31:0] p;
    
reg [31:0] p;
reg [15:0] temp1, temp2;
     
always @ ( a or b)
begin
 
temp1 = (a - 1);
temp2 = (b - temp1);
 
p <= {temp1|temp2};
end
endmodule
 
Last edited by a moderator:

p <= {temp1|temp2};
Click to expand...

You do realize that isn't concatenation in binary but is a bitwise OR of temp1 with temp2. Concatenation is done as follows
Code Verilog - [expand]
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p <= {temp1, temp2};

But this will result in (temp1 * 2^16 + temp2), which isn't what want.

The calculation you want isn't trivial as it requires knowing the value of temp2 so you can multiply the temp1 value with a multiple of 10 to shift the temp1 value to the next digit position then add the two values together to get your result. So you need to know ( temp2<16'd10, temp2<16'd100, temp2<16'd1000,...etc) and multiply temp1 accordingly.

You've also mixed blocking and non-blocking statements in your always block. You'll need to fix that if you want this code to work correctly.

Regards,
 
Thank you ads-ee. That helped. I'm new to verilog coding. I rectified the blocking and non blocking statements also.
 

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