O(i) is a single bit. You still have not created an array of ufixed.
And what you are doing is way more complicated that it needs to be. You can do a rightshift without a clock.
Yes, my input is an array of integer (with unspecified size) and I want to multiply the input with a fixed point. My previous post is just an example;
input, f= (12,3,10,7). Then, multiply the input with 0.25.
I never plays with decimal number(floating foint) before. I have read books/materials about this topic and I try to write a code for better understand. But, I become more confius now.
My idea is first to convert the integer array to ufixed since it cannot multiply directly wth 0.25. I'm sorry if I ask for a stupid question, I just want to learn. Thanks for reply
The below code does what you are asking for. But is doesn't make much sense in my opinion.
Code:
package my_data_types is
type exam is array (natural range <>) of integer;
end my_data_types;
Library IEEE;
use IEEE.std_logic_1164.all;
use work.my_data_types.all;
use IEEE.numeric_std.all;
entity fix is
port (A: in exam (1 to 8);
O: out exam (1 to 8));
end fix;
architecture fix of fix is
begin
process (a)
begin
for i in 1 to 8 loop
o(i) <= a(i)/4;
end loop;
end process;
end;
I have write a code using fixed_pkg. It compile successfully in quartus, but when I try to simulate in ModelSim an error occur.
---------------------------------------------------------------------------------------------------------------
library ieee;
library ieee_proposed;
use work.fixed_pkg.all;
use ieee.numeric_std.all;
entity fix is
port (clk: in bit;
nprev: in integer range -127 to 127;
ip1: out ufixed (8 downto -9));
end fix;
architecture fix of fix is
signal n1: ufixed (4 downto -4);
begin
process(clk)
begin
if (clk'event and clk='1') then
ip1 <= (to_ufixed(0.483,n1)) * (to_ufixed(11,n1));
end if;
end process;
end fix;
----------------------------------------------------------------------------------------------
This is the error in ModelSim:
# Compile of fix.vhd failed with 2 errors.
# Compile of fix_tb.vhd failed with 2 errors.
# Compile of fixed_float_types_c.vhdl was successful.
# Compile of fixed_pkg_c.vhdl failed with 1 errors.
# Compile of fixed_synth.vhdl failed with 2 errors.
I have add all the fixed_pkg in the project (in quartus). Need your helps..
---------- Post added at 08:49 ---------- Previous post was at 08:45 ----------
This the error when I expand it:
** Error: H:/altera/mul_try_tb/fix_tb.vhd(2): Library ieee_proposed not found.
Sorry, what do you mean by this word: Also, do NOT add any of the floatfixlib to the work library.
---------- Post added at 12:41 ---------- Previous post was at 12:31 ----------
I use ModelSim Altera Starter Edition 6.6
---------- Post added at 12:56 ---------- Previous post was at 12:41 ----------
After I remove the ieee_proposed library, this error occur in ModelSim:
# Compile of fix.vhd failed with 2 errors.
# Compile of fix_tb.vhd failed with 2 errors.
# Compile of fixed_float_types_c.vhdl was successful.
# Compile of fixed_pkg_c.vhdl failed with 1 errors.
# Compile of fixed_synth.vhdl failed with 2 errors.
** Error: H:/altera/mul_try_tb/fix.vhd(3): Library floatfixlib not found.
** Error: H:/altera/mul_try_tb/fix.vhd(4): (vcom-1136) Unknown identifier "floatfixlib".