Debugging help needed for Xilinx FPGA

Vivado is an entire rewrite by a different team of software engineers than ISE. The synthesis engine was purchased by Xilinx a number of years back. The tool uses a single executable with much better memory management of the database, hence it's faster and less of a memory hog when running large designs on large parts.

So no it's not anything like an evolved version of ISE.

Thanks for sharing. I haven't been following up FPGA stuff for years, so not aware of this.
Anyway, do you know if possible flaw in Vivado flow?

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Vivado is an entire rewrite by a different team of software engineers than ISE. The synthesis engine was purchased by Xilinx a number of years back. The tool uses a single executable with much better memory management of the database, hence it's faster and less of a memory hog when running large designs on large parts.

So no it's not anything like an evolved version of ISE.

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Vivado synthesis is new (or less than 2 years old) so yes there are more than likely bugs lurking in it. Have you tried isolating your module into a separate design (with some interface to the pins, so it doesn't get removed) and see if the problem only occurs when the entire design is built or just your portion. Depending on the result it may be something that you'll have to open a support ticket with Xilinx. If happens to your portion of the design only, then it may be a problem with the synthesis of your code with the options used (as it seems to synthesize and build correctly at 40 MHz) or you are using a old speed file.

Make sure you are using the latest speed files for the device. And before you ask no I have no idea how to find out if you have the latest. I've traditionally just updated the tools to the latest version or asked the FAE if there was a newer speed file out for the device I was using.

Once again you never mentioned what device/speed grade/Vivado version you are using. Vivado is currently at version 2014.4.