Debounce circuit for push button

Hi, I need to set 100 ms time constant. I have found this debounce circuit. Can someone please explain this circuit and help me to find the values of Rp1 and R1 and also the value of capacitor such that I should 100 ms time constant ?

That is not a good way to debounce a mechanical key closure.

Most often debouce done in code.

There are processors in market that have HW debounce facilities inside them



Attached code examples and basics.


Regards, Dana.

Hi,

by pressing the button you are partially discharging the capacitor (Q = C \[\cdot\] V). The 1 k\[\Omega\] resistor in parallel to your capacitor keeps the voltage at the capacitor at \[\frac{{V}_{cc}}{ 11}\] . By releasing the switch your capacitor is now charged again, starting from \[\frac{Vcc}{ 11}\] with the time constant \[\tau = {R}_{p1}\cdot {C}_{1}\]. Now you have to adjust your values to meet your desired time constant. Keep in mind your capacitor is pre-charged when releasing the switch. You can calculate the voltage by

\[{V}_{C} = \]\[\frac{{V}_{cc}}{11 } + \]\[\frac{{V}_{cc} \cdot 10}{11 } \cdot \]\[\left( 1 - {e}^{- \frac{\tau}{R \cdot C }}\right)\].

You have to check the on-threshold level of your MCU. So you have to choose your values in a way that \[{V}_{C }\] does not exeed this threshold value for 100 ms.

BR

The capacitor should have a value in accordance with the input leackage current of your MCU and can be determined by

\[C = \frac{{I}_{\mathrm{leackage}} \cdot 100 ~\mathrm{ms}}{ \Delta V}\].

Where \[\Delta V\] is the maximum allowed voltage deviation during the 100 ms e.g. 0.5 V.

BR

The shown capacitor calculation is usually used if a SPDT switch is used and pressing the switch is causing a connection either to Vcc or GND.

Hi,

There is a rising time constant and a falling time constant. Which one do you mean?
Sure you mean time constant? ... which is R x C .... or do you mean delay (time)?

Klaus

The method proposed is not a good idea. This is a sim of noise
in system still affecting jitter on gate output. I had to inject the
noise via ground leg cap because could not figure out how to
make the Vcc noisy. Noise was set at 100 mV RMS, typical in a 5V
system.

Keep in mind noise is input referred from Vcc noise thru Rdson
of pmos in totem pole and Cgd, and of course switching ground
bounce noise.

Not accounted for is imperfect C used to suppress bounce, eg,
its L and parasitics.

As you can see output jitters which is wholly undesirable.




On another matter, depending on how power supply collapses, C discharges
thru input protection diodes. Possible peak currents can cause silicon damage,
its not recommended to directly connect large C to CMOS pins for that reason.


Regards, Dana.

An example w/o significant C, 100 mV RMS of noise. Look at your Vdd
supply rail with scope, turn on scope infinite persistence, to see the
pk-pk noise you have in your design. Basically one does not want slow
rise/fall times in CMOS, or any other logic family for that matter that
has un-conditioned inputs (like with Schmidt trigger for example).





**broken link removed**

Some excellent scope captures of the problem



Regards, Dana.

Hi, I have found this RC debouncing circuit. If R1 = 10 K and R2 = 1 K and I need around 100 ms time constant then what should be the value of the C ?

I also need to understand the attached circuit.

If the button is released, then R1 = 10 K, R2 = 1 K and C will all be in series. The C will start charging from Zero. How much voltage will be there across C after the time constant ? I guess the charging time constant will be (R1 + R2) x C, right ? but what will be the voltage after that constant ?

If the button is pressed, then I guess C will start discharging through R2. The discharging time constant will be R2 x C, right ? but what will be the voltage after that time constant ?

In my application I need large time constant because the switch is pressed and released slowly. Even 200 ms time constant is also fine. I would like to read the switch in the MCU with a delay of 200 ms to avoid false reading.

joniengr said:

I would like to read the switch in the MCU with a delay of 200 ms to avoid false reading.

Click to expand...

It's easy to do in software.
Detect the first switch signal change (bounce), then delay the response to another input (bounce) until after the desired time (100-200ms).

Hi,

As already mentioned in post#4:
* there is a falling time constant (discharge current only flows through R2)
* and a rising time constant (charge current flows through R1 and R2)

Klaus

In post #6 there are two ap notes basically telling us NOT to use
slow rise/fall times of signals into CMOS. Here is another reference -


If you have to do the debounce external,. not in code (as normally done) then use a Schmidt trigger
between the RC network and the CMOS input. You can get single gate logic Schmidt triggers here -





There is one other consideration. If a large C is attached to a CMOS I/O pin, if
supply collapses, turns off, under certain situations the large charge on the cap
discharges thru internal parasitic PN junctions, and can cause a hot spot to occur
in the silicon possibly damaging or altering the parts functionality.

NOT A GOOD IDEA


Regards, Dana.

Hi,

danadakk said:

In post #6 there are two ap notes basically telling us NOT to use
slow rise/fall times of signals into CMOS. Here is another reference -

Click to expand...

Usually I agree with your posts.
But regarding noise in post#6 I think it is not realistic.
In post#6 the "source" of noise seems to be the capacitor, since the noise generator is connected in series with the capacitor.

In a real circuit the noise caused by the capacitor surely exists, but should be negligible small.

The meaning of the capacitor in the circuit is to "suppress" noise.
The noise usually comes from outside via the resistor ... maybe the unshielded cabling...
The capacitor should be connected close to the target (microcontroller) with low impedance connection to the GND plane.

Klaus

The noise is a combination of conducted thru miller, from primarily
the Vdd supply rail, and the ground bounce created as both devices in
totem pole turn on. Thats confirmed by the TI ap notes as well. Other CMOS
logic manufacturers discuss this as well in their logic handbooks. Additionally
one can think of the noise as input coupled if so desired. The oscillator guys
also talk about this with regards to affecting jitter performance.

I only fed the noise thru the cap because i could not figure out how to override
the sim I was using and its inaccessible logic Vdd supply, which is where I would have
put the noise gen. But its input referred so its a legit way. Its easy to replicate the
problem on the bench with a noise source and a ramp generator.


Regards, Dana.

Hi,

Oh,the capacitor you show is the "gate internal" capacitor.
But then you ignore that there is a much bigger external capacitor.

If you further go into details:
* a proper GND plane
* a properly installed power supply decoupling capacitor will improve noise bahaviour.
On the other hand
* series impedances in GND, VCC and signal input lines make the situation worse.
Thus one needs to keep them low.

If there still will be some additional output transitions, they will be relatively fast, won't take long, maybe don't reach full voltage levels.
Whether this causes problems depends on how the signal is processed.
I doubt a "microcontroller poll" will cause problems in reality.
The worst may be if the signal is used as counter input clock, which counts every transition...

Although I have to admit that a schmitt trigger is the "safe" solution ... I'd say in most cases it not necessary.

Klaus

The cap is the external cap used to "debounce" the input by slowing
Tr and Tf. I see I used 10 nF, should have used .1 and 1K like the original
posted. The reference to miller cap is the notion of looking at this as input
referred noise from the transition in the totem pole, as well as the noise I
injected thru the external cap. I could have injected noise thru an R, where
the noise comes from produces the same results. And miller couples the
transient created from totem pole both N and P MOS on simultaneously.

Here is a sim with posters original values, results essentially same.



" I doubt a "micro controller poll" will cause problems in reality. " I would have
agreed with this years ago, except we now have processors executing instruc-
tions < 1 uS which can cause polling, if not done right, to fail.

As you point out L compounds the problem, and the L in bulk caps so much more
problematic, eg. larger parasitic. And the sub micron geometrys now being used
in chip internal transistors makes them more sensitive to noise. The Logic handbooks
discuss transistor speed versus safe Tr and Tf.

And then we have the issues of dumping these bulk caps charge thru internal PN
junctions during power off which Rel departments are very much aware of. Back in
the early 80's if my memory serves me.


Regards, Dana.