Dead time in MC34025 SMPS full bridge driver?

[grizedale]

Hi,

Why would anyone need to worry about dead-time in a MC34025 full-bridge controller?

The MC34025, in fig 24, page 11, gives a way of increasing the dead time for MC34025......

MC34025 DATASHEET:
https://www.onsemi.com/pub_link/Collateral/MC34025-D.PDF

...but page 3 of the MC34025 datasheet states that the maximum duty cycle of each output is 45%......so in a 100KHz converter, each fet is ON for a maximum of 9us......then there is a gap, when neither fet is on, for 1us....then the other fet is switched on.

..so that's 1us gap between the bottom fet switching off and the top fet switching on....so why do we need to worry about dead-time.?

 

[mtwieg]

That IC implements dead time between the two outputs, which is necessary for half bridge or push pull converters. The dead time is determined by the width of the clk pulse, which is in turn determined by Ct. For a full bridge, you don't need dead time between the two outputs (which should each be controlling one half bridge), but rather you need dead time between the switches within each half bridge. This controller can't provide that, so it needs to be implemented externally.

 

[atripathi]

I think it provides you a flexibility to add additional dead time. How much dead time you need could be a function of circuit and 5% duty cycle dead time may not be sufficient. This allows you further increase the deadtime.

 

[grizedale]

Thanks.

mtwieg: Though Ct does not affect dead-time in MC34025.
The datasheet confirms this
-i dont see why external dead time is required.

...the duty cycle is max 45%.....so at 100KHz, (bridge frequency, as opposed to fet frequency, in a full bridge) that gives a one second gap between top fet going off and bottom fet coming on.

-that should be enough...why is extra dead time recomended by the fig24 , page 11?

 

[mtwieg]

Thanks.

mtwieg: Though Ct does not affect dead-time in MC34025.

It certainly does. It doesn't affect the maximum duty cycle, (unless you alter the charging/discharging currents), but it does change frequency and thus duty cycle. Actually that's a pretty odd way to build an oscillator, it's like they're deliberately trying to make it difficult to control the dead time independently of frequency.

-i dont see why external dead time is required.

...the duty cycle is max 45%.....so at 100KHz, (bridge frequency, as opposed to fet frequency, in a full bridge) that gives a one second gap between top fet going off and bottom fet coming on.

-that should be enough...why is extra dead time recomended by the fig24 , page 11?

Post a simple schematic of how you'll interface that controller with a full bridge converter. I'm almost certain that you're planning to use it in a way where the dead time provided by the controller isn't useful (or even necessary).