Ddr4 data lines routing

[Dinesh2017]

Now i am working on DDR3 board its has 8 layer frequency range(1066 MHz). stripline used for signals routing. my doubt is one side full GND reference plane will be there and other side PWR split plane will be there. so signals crossing split plane any problem occur or it will work out.please clarify
my doubt

 

[shaiko]

It doesn't really matter if the plane is ground or Vcc - do not route high speed signals over split planes.
This is because split planes present impedance discontinuities that are impossible to terminate properly and will therefore degrade signal integrity.

Regarding Striplines - they produce less crosstalk than Microstripes so for high speed signals they're a clever choise (as long as you keep the number of vias to a minimum).
Try to route DDR signals (or any other critical pass for that matter) first. This way it'll be easier to meet the strict layout requirements.

 

[FvM]

If the split planes are massively bypassed to a continuous ground plane, the impedance discontinuity may be acceptable though.

 

[Dinesh2017]

Hi,

i have one reference board in that board they run over split plane ddr signal . i read some document same thing mentioned in that document should not route in above split plane.but i discuss with circuit designer low frequency we can run.can you some ref notes.

 

[shaiko]

Signal integrity has more to do with slew rates than actual frequency.
But yes, "slow" changing signals are more tolerant to impedance mismatches.

If your evaluation board has critical DDR3 paths routed over split planes - I wouldn't use the layout for reference without extensive SI simulation. Even if it's fully functional.

 

[Dinesh2017]

Hi sir

thanks for valuable reply .

16 bit ddr3 working. so 0 to 15 data line will be there i cant able to route all in same layer .so shifted to next layer i know it will create some problem .my doubt is what kind of problem it will create or we can do route like that can you explain.

my problem is i am working small company without knowing i am doing layout .please help me

 

[ads-ee]

You can route DDR3 DQs and DQSs on multiple layers, the critical requirement is the trace lengths of all the DQ pairs and the DQSs in a byte lane should all be matched. I would try to keep the DQ and DQS for a byte lane on the same layer, though it's probably not going to affect much if you don't. When routing the DQ and DQS try and keep the DQS as the reference length and keep all the DQ lengths +/- some mils around that reference. If they aren't matched properly you may find your DDR3 never gets out of calibration. Be very careful of the delay between the control and DQs if you are using an FPGA to drive the DDR3 as the requirements of the FPGA controller are likely to be tighter than the DDR3 specification (Xilinx is certainly much tighter). At 1066 you probably won't need to take the package delays into account.

A split plane is bad primarily if they are the only reference planes for a signal crossing the split (i.e. microstip over split planes is really bad). That signal then has no return current path. If there is a unsplit ground plane adjacent to the signal then the return current will go through that plane avoiding the split plane altogether. Basically this means if you want better signal integrity for signals in a split_plane - sig_layerl1 - sig_layer2 - Gnd_plane configuration you would want to route those signals on sig_layer2 and only slow or static signals on sig_layer1. Even the sig_layer1 will be somewhat okay as the lowest impedance return path will likely still be through the ground plane, but it will affect the signal integrity of that signal.

 

[Airbag79]

It doesn't really matter if the plane is ground or Vcc - do not route high speed signals over split planes.
This is because split planes present impedance discontinuities that are impossible to terminate properly and will therefore degrade signal integrity.

Regarding Striplines - they produce less crosstalk than Microstripes so for high speed signals they're a clever choise (as long as you keep the number of vias to a minimum).
Try to route DDR signals (or any other critical pass for that matter) first. This way it'll be easier to meet the strict layout requirements.

1.) If you're under 1 GHz, you may be able to get away with routing on VDDQ and VSS. Albeit, if you share VDDQ and VSS as reference planes for a stripline TL, the only path for the return-current is the through the VDDDQ-VSS (plane plane) impedance. This will generate ground bounce, since VSS/VDDQ are DC isolated. A popular myth is if the two planes are AC coupled properly, the return current will pass through the decoupling capacitor, but this is typically not the case. As signal return current takes the path of least impedance, and capacitors are usually at a higher impedance due to mounting inductance and exacerbated by signal edge-rates.

2.) Not true. Stripline is is inherently less susceptible to FEXT (due to homogeneous dielectric), albeit, you can still have bad crosstalk with either ustrip or stripline. XTALK is all about proximity. Mutual L and mutual C. If ustrip is routed properly, it can outperform stripline. It depends on numerous variables.

- - - Updated - - -

Signal integrity has more to do with slew rates than actual frequency.
But yes, "slow" changing signals are more tolerant to impedance mismatches.

You're confusing TDR with overall Return Loss. The impedance magnitude of a discontinuity (via, pad launch, etc) is directly proportional to the edge-rate, as faster dv/dt equates to higher harmonic content. If you have split-plane in the return path on a common-mode signal (single-ended) whether it's fast or slow, there will be a substantial impedance bump which will not only impact the Return Loss (Reflections) but will also generate XTALK and EMI. The bigger issue is the generation of XTALK and EMI over a void. Especially in a densely routed parallel bus.

 

[shaiko]

2.) Not true. Stripline is is inherently less susceptible to FEXT (due to homogeneous dielectric), albeit, you can still have bad crosstalk with either ustrip or stripline. XTALK is all about proximity. Mutual L and mutual C. If ustrip is routed properly, it can outperform stripline. It depends on numerous variables.

I meant that Sriplines are less susceptible to backward crosstalk while uStips are susceptible to both forward and backward crosstalk.
Of course spacing plays a key role.
But if you compare a Stripline to a uStrip - the former will have better crosswalk immunity.

You're confusing TDR with overall Return Loss. The impedance magnitude of a discontinuity (via, pad launch, etc) is directly proportional to the edge-rate, as faster dv/dt equates to higher harmonic content. If you have split-plane in the return path on a common-mode signal (single-ended) whether it's fast or slow, there will be a substantial impedance bump which will not only impact the Return Loss (Reflections) but will also generate XTALK and EMI. The bigger issue is the generation of XTALK and EMI over a void. Especially in a densely routed parallel bus.

Not sure why you think I confusing one with the other - I said something very simple...

Suppose you have a PCB trace that travels across through 22 board layers dives inside 33 vias and jumps 44 discontinuous planes.

Now drive this trace with:
1. 3.3V (1V/ns) pulse.
2. 3.3V (1V/ms) pulse.

Observe the Rx side with an Oscilloscope - which one would look better ?

 

[Airbag79]

I meant that Sriplines are less susceptible to backward crosstalk while uStips are susceptible to both forward and backward crosstalk.
Of course spacing plays a key role.
But if you compare a Stripline to a uStrip - the former will have better crosswalk immunity.


Not sure why you think I confusing one with the other - I said something very simple...

Suppose you have a PCB trace that travels across through 22 board layers dives inside 33 vias and jumps 44 discontinuous planes.

Now drive this trace with:
1. 3.3V (1V/ns) pulse.
2. 3.3V (1V/ms) pulse.

Observe the Rx side with an Oscilloscope - which one would look better ?

Again, this is simply not true. It depends on numerous variables.

- - - Updated - - -

Not sure why you think I confusing one with the other - I said something very simple...

Suppose you have a PCB trace that travels across through 22 board layers dives inside 33 vias and jumps 44 discontinuous planes.

Now drive this trace with:
1. 3.3V (1V/ns) pulse.
2. 3.3V (1V/ms) pulse.

Observe the Rx side with an Oscilloscope - which one would look better ?

Any common-mode signal above 1 MHz that encounters a return plane void will generate substantial XTALK in addition to poor Return Loss, irrespective of edge-rate (relatively speaking).

Edge-rate is more "important" wrt poor impedance match of a structure/TL. Messing up the return current path is a special case of discontinuity, it's important to differentiate this from just poor impedance match of the signal path structure, i.e. a via that's not 50 ohms. Where edge-rate plays a significant role in the magnitude of the discontinuity due to harmonic frequency content.

 

[shaiko]

The second paragraph of #9 ended with a very simple question - You didn't answer it...

 

[Airbag79]

The second paragraph of #9 ended with a very simple question - You didn't answer it...

I wonder why...Your assumption of absolutes and only considering single variables is misleading. I'm not attempting to pontificate with you, only augment the fact that oversimplifying complex topics is ambiguous.