DDR3L signals and decouple caps

Hi all,

I have some questions regarding DDR3L.
I have a lot question because i'm new to DDR3L SDRAM. (I reed the datasheet of the memory but didn't understand all the signals and there is no decoupling scheme in the datasheet)

What are these signals: Data_Mask, Data_Strobes, ICLK_DRAM_TERM(100k to gnd), DRAM_VDD_S4_PWROK, DRAM_CORE_PWROK, ZQ, ODT, DRAM_DQSP(UDQS, LDQS) ?

And are there some papers how to and how many decouple and baypass caps to use on DDR3L memory chip?

Best regards.

See any Manufacturer app notes like micron for decoupling caps....
These signals looks like DDR4 signals.....

In general, regarding bypass capacitors: Whatever values are recommended by the chip manufacturer, it is worth noting, that type and physical size as well as distance between chip and bypass capacitor and grounding are at least equally important.

On circuit board, the placement of capacitors should be very close to the chip's power pin(s), with as short as possible way to the same chip's ground connection(s).

Therefore, see also recommended circuit board layout, and use physically small chip capacitors: The smaller size ones have in general smaller stray inductance, than larger ones (avoid especially through-hole capacitors with wire - they are very inductive).

Very often you have to use also two quite different values in parallel: Smaller value for fastest transients, and larger one for managing slower variations. That is because every capacitor has a resonance frequency, and above that they behave more or less like inductors - and their impedance is thus increasing on frequencies above the resonance. Large values have a lower resonance frequency, and smaller values have it higher. Also, physically larger capacitors have higher inductance.

In my experience, for high speed chips the circuit board layout is also as important as the capacitors themselves. Both have to be considered simultaneously.