ddr3 sodimm daughter board for haps-80 system

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david-edaboard

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Is the sys_clk of MIG is provided by the ddr3 sodimm board?
what is the frequency of the clk provide by the ddr3 sodimm board?
and what is the io standard of this signal? thanks!
 

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@david-edaboard
Did you read the spec of the MIG IP core from Xilinx?
I think it is mentioned there in the section where they tell you step-by-step how to configure the core:
 

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