DDR3 micron simulation help

[yuvalkesi]

Hi,
I'm trying to simulate the DDR3 along with Micron model in Modelsim but no luck.
I keep getting this error:
# tb.sdramddr3_0.file_io_open: at time 0.0 ns WARNING: no +model_data option specified, using /tmp.
# ** Warning: (vsim-3533) [FOFIW] - Failed to open file "/tmp/tb.sdramddr3_0.open_bank_file.0" for writing.
# No such file or directory. (errno = ENOENT) : E:/user/ddr_sim/ddr3.v(622)
ANy help from someone who did it?
Thx,
Ron

 

[ads-ee]

From the warning it looks like it can't open the tb.sdramddr3_0.open_bank_file.0 in the /tmp directory. Is that directory write protected or non-existent?

 

[yuvalkesi]

From the warning it looks like it can't open the tb.sdramddr3_0.open_bank_file.0 in the /tmp directory. Is that directory write protected or non-existent?

Thanks for your reply.
First, this directory does not exist, so I created it (didn't help, though), but still - tb.sdramddr3_0.open_bank_file.0, there's no such file. The open_bank_file is a function generated inside ddr3.v file, and it is surely not a filename, so I don't understand how it bacame a filename. I can add the code for you to see if you want...

 

[ads-ee]

Sure post the code, I or someone else might have some insight as to what is going on.

regards

 

[yuvalkesi]

Hi,
Attached.
look for 'open_bank_file' function.
Thank you!

 

[mrflibble]

/tmp would be a typical unix path. If you're a windoze user then you should change that /tmp directory to something that does exist on your system. E:\user\ddr_sim for example, if that's appropriate in your case.

 

[yuvalkesi]

Ok, did it...
now Modelsim shows this:
** Warning: (vsim-3533) [FOFIW] - Failed to open file "e:/user/abc/ddr_sim//tb.sdramddr3_0.open_bank_file.0" for writing.
# No such file or directory

where is it getting its filename from???

Thanks

 

[mrflibble]

And does directory "e:/user/abc/ddr_sim actually exist on your system?

It gets the filename from that testbench no doubt. I see a couple of "open_bank_file" references in there.

 

[yuvalkesi]

Of course...
What I don't understand is where does it get its filename "tb.sdramddr3_0.open_bank_file.0" from.
It put brackets on it as if it was a filename.
The sdramddr3_0 is the intantiation module name. It is not a filename. The open_bank_file is a function. It is not a filename.

 

[mrflibble]

Of course...

Heh, to you this may be "of course". To me, I never assume such trivial stuff has actually been checked on the other side of the screen. In fact, I currently still am not 100% convinced, given the error message.

The sdramddr3_0 is the intantiation module name. It is not a filename. The open_bank_file is a function. It is not a filename.

I noticed it was not a filename. But as said, the testbench does have that direct reference in it, which is round about zero coincidence. Up to you (or someone else who feels like it) to trace it down a bit further in that testbench. Or by running the testbench and checking the variables...

Also note the double slash in that filename. Shouldn't be an issue per se, but it might be indicative of an empty string used while building up the path name. Just something to be aware of.

 

[ads-ee]

The file name being created is "0" with a %m tacked on in front of it (lists the hierarchical path).

---

Code Verilog - [expand]
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// this sets the filename for writing:
    initial
    begin : file_io_open
//...
        for (integer i = 0; i < `BANKS; i = i + 1)
            memfd[i] = open_bank_file(i);
 
 
// this function opens the file:
    function integer open_bank_file( input integer bank );
        integer fd;
        reg [2048:1] filename;
        begin 
            $sformat( filename, "%0s/%m.%0d", tmp_model_dir, bank ); // filename is constructed from these items.
            fd = $fopen(filename, "wb+");

---

I've left out a bunch of extraneous stuff that doesn't really make a difference.

My suggestion is change the $sformat line to something that makes more sense on a windows machine (like a format string of "bank_file_%0d" which will leave it in the simulation directory. You can later play around with moving it to some other output directory after you get it working.

BTW, It might be useful if you do some reading on Verilog file I/O system tasks. Most of this would have been easy for you to figure out if you had the background in using those system tasks. It's worth the effort of learning as it comes in handy when you need to capture data in your testbench.


regards