DDR3 Address Lanes Impedance

Hi,

I guess the "mismatched" trace is very short.
If it is less than lambda/10 then it´s not critical at all.

Klaus

KlausST said:

Hi,

I guess the "mismatched" trace is very short.
If it is less than lambda/10 then it´s not critical at all.

Klaus

Click to expand...

Dear Klaus,
Thank you very much for your answer. Actually, it will also help me to route traces with narrower widths. So if my intuition is right, it will help me to prevent reflections, also I can route traces narrower.

Hi,

For sure there may be in improvement when you use two 80 Ohm lines (quasi in parallel) to get 40 Ohms.
May I ask where your termination resistor is placed?

Ideally it should be at the end of the line to get no reflections. But I guess this is not possible.

Address lines usually are one direction only:
Thus the signal is sent by the MCU (FPGA) and received by the RAM.
So the way is:
Transmitter --> trace --> branch -> RAM (here the timing for the mismatch effect is too low to cause a problem, but I also guess the echo voltage is too low to cause problems) --> then it goes back all the way to the transmitter (where it causes no problem but gets reflected again, if not terminated properly) ---> then the echo travels back to the ram (again reduced in voltage) --> at the RAM now the echo timing may be critical to cause problems, but the voltage should be too low.

Depending on rise rate, trance length... I guess the mismatch (echo) voltage is in the range of some millivolts only.

Klaus