DDR2 trace length matching

Hi - I am looking to layout a PCB that has two Issi IS43DR16320C-3DBL DDR2 SDRAMs. See here for the datasheet.

They are connected with the addresses together and one chip provides my lower two bytes and the other provides my upper two bytes.

I've been reading up on laying out DDR2 on PCBs and I'm getting a lot of information that sort of matches, but not quite. For example, Altera says:

-All data, address, and command signals must have matched length traces ±50 ps (±0.250 inches or 6.35 mm)
-All signals within a given Byte Lane Group should be matched length with maximum deviation of ±10 ps or approximately ±0.050 inches (1.27 mm) and routed in the same layer

Micron says:

A good startingpoint is keeping all traces within a byte lane between 15–20ps. This includes all data lines and the associated strobe. Timing between different byte lanes can usually be a bit more relaxed and are typically within
60–70ps.

But what is not entirely clear is which signals are in which bytes lanes. Here's my best understanding of it:

Byte lane 0: D0-D7 (1), LDQS/nLDQS (1), LDM (1)
Byte lane 1: D8-D15 (1), UDQS/nUDQS (1), UDM (1)
Byte lane 2: D0-D7 (2), LDQS/nLDQS (2), LDM (2)
Byte lane 3: D8-D15 (2), UDQS/nUDQS (2), UDM (2)

Where the numbers in parentheses are the chip numbers. But I'm not sure which, if any, byte lane the address lines, clock lines, bank lines, etc fall into. I found this document that talks about "signal classes". Table 5 on page 21 suggests 7 different net classes. 4 of them match what I have above, 1 has the other lines I mention above, then the remaining two I'm not sure about.

So from that document I'd think that my final byte lane is:

Byte lane 5: A0-A12, BA0-BA1, nCAS, nRAS, CK/nCK, nWE, and nCS

With that in mind - I would then just lay it out making sure that my longest trace within a byte lane is no more than 2.54mm longer than the shortest trace in that byte lane, and that the longest of any DDR2 traces is no more than 12.7mm longer than my shortest trace in any byte lane.

Does that all sound OK? One last thing that bothers me - none of these datasheets mentions what speed the DDR2 is operating at. Why does the speed not matter?

Thank you so much for your help!!

You have data lanes that consist of:
Data lines, data strobe, and data mask, usually with a D in the signal name
You have an address bus, usually labelled A in the signal name.
You have a control bus RAS, CAS WE etc
And finally you have the clock signals, CKn and CKp.
The clock and data strobe signals are diff pairs.
The clock pair has to be the longest signal.
Route data lanes on same layer in each group, match to 0.050", between lanes 0.500".
Address lane skew 0.200"
Control lane skew 0.200"
This is just off top of my head, I would suggest you search this forum for DDR2 as we have discussed it many times, I did use to have a one page sheer that explained it all but cant find it at the moment.

With that in mind - I would then just lay it out making sure that my longest trace within a byte lane is no more than 2.54mm longer than the shortest trace in that byte lane

Click to expand...

No, 0.050" (1.27mm) is the maximum allowable skew between traces within one data lane.