ddr2 batch simulation

Status
Not open for further replies.

balamani

Member level 1
Joined
Jan 11, 2013
Messages
38
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,554
Hi

I have done a DDR2 signal integrity-batch simulation using hyper lynx 8.2.1

I got the attached excel sheet after the simulation.

On what basis the following parameters are measured and compared? Are there any standard values to compare? Please explain.

Rise Min Delay [ns]
Rise Max Delay [ns]
Rise Ref Time-to-Vmeas [ns]
Fall Min Delay [ns]
Fall Max Delay [ns]
Fall Ref Time-to-Vmeas [ns]
Flight Time Comp. [Yes/No]
Rise Rail Overshoot [mV]
Rise Dynamic Rail Overshoot Time [ps]
Rise SI Overshoot [mV]
Fall Rail Overshoot [mV]
Fall Dynamic Rail Overshoot Time [ps]
Fall SI Overshoot [mV]
Ringback Delay [ps]
Rise Closest Ringback [mV]
Fall Closest Ringback [mV]
Rise/Fall Multi Cross [Pass/Fail]
Rise/Fall Delay Error [Pass/Fail]
 

Hello,

Have you used timing budget calculation between processor and ddr2 using datasheets ? If yes, then you must be aware of delay calculation.

These results are based on applied timing value and values given in IBIS model. Generally, all DDR devices follows JEDEC standard. and all values are according to JEDEC standard only.
Please have a close look in IBIS model. voltage levels define overshoot/undershoot. Ramp dv/dt defines rise/fall time.
 

Status
Not open for further replies.
Cookies are required to use this site. You must accept them to continue using the site. Learn more…