DDR Serial-In Parallel-Out Shift Register Verilog Code

er.akhilkumar · 2024-11-08T10:09:07+0000

Hi,

I have a situation where I need to capture Serial DDR data and convert it into a parallel output. In this case, I need to use two sequential blocks, one working on posedge of clock and another working on negedge of clock, then I need to merge this data. What is the best way to achieve this in Verilog? Please guide.

Thanks.

KlausST · 2024-11-08T10:13:54+0000

Hi,

.. I guess a single DFF to (time wise) align the one data straem to the other.

But without any details it is what it is: A guess.

Klaus

kaz1 · 2024-11-08T12:23:49+0000

er.akhilkumar said:
Hi,

I have a situation where I need to capture Serial DDR data and convert it into a parallel output. In this case, I need to use two sequential blocks, one working on posedge of clock and another working on negedge of clock, then I need to merge this data. What is the best way to achieve this in Verilog? Please guide.

Thanks.

You have two sections; DDR to one clock edge & serial to parallel.

For DDR read this document to see how Intel(Altera) done it:
Google: ALTDDIO megafunction user guide

DDR Serial-In Parallel-Out Shift Register Verilog Code

er.akhilkumar

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KlausST

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kaz1

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DDR Serial-In Parallel-Out Shift Register Verilog Code

er.akhilkumar

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