DDR Serial-In Parallel-Out Shift Register Verilog Code

[er.akhilkumar]

Hi,

I have a situation where I need to capture Serial DDR data and convert it into a parallel output. In this case, I need to use two sequential blocks, one working on posedge of clock and another working on negedge of clock, then I need to merge this data. What is the best way to achieve this in Verilog? Please guide.

Thanks.

 

[KlausST]

Hi,

.. I guess a single DFF to (time wise) align the one data straem to the other.

But without any details it is what it is: A guess.

Klaus

 

[kaz1]

Hi,

I have a situation where I need to capture Serial DDR data and convert it into a parallel output. In this case, I need to use two sequential blocks, one working on posedge of clock and another working on negedge of clock, then I need to merge this data. What is the best way to achieve this in Verilog? Please guide.

Thanks.

You have two sections; DDR to one clock edge & serial to parallel.

For DDR read this document to see how Intel(Altera) done it:
Google: ALTDDIO megafunction user guide