DDR SDRAM routing questions

)ddr memory routing

Hi!
I`m currently work on project with DDR SDRAM on-board.
I use 4xSDRAM chips (x16 width) in 64 bit memory subsystem
and have four group of CK/CK#, DM(), DQ(), DQS() signals
But I can`t find any recomendations about DDR SDRAM routing
(CK/CK#, DM(), DQ(), DQS() traces length in group, traces skew
between group, etc.)

I`m try to find info in WWW, but all recommendation that I find is about routing
DDR SDRAM I/F from one chip on board (like CPU) to DIMM socket. But I have
SDRAM chip onboard.

Can anyone share experience for DDR SDRAM routing?

***
Regards, BJ

see board design guidelines part of altera an348.

**broken link removed**
http://www.altera.com/technology/memory/sdram/mem-ddr_sdram.html

Hi BJ,

https://developer.intel.com/products/chipsets/

Intel 855GME ----> https://www.intel.com/design/chipsets/embedded/855gme.htm



just download any of the current guide for Intel chipsets, it has guide for DDR memory routing strategy.

regards,
newbie

If u perporm timing anlysis for ur Driver to DDR interface u came to know how much maximum length u can give for ADD,DQ,DQS signals inorder to meet the setup and hold time requirements.

As i understand from you ,
1) You have a chip on your board that is going to drive the memory bus,
2) and SDRAM modules directly attached to board, or to put in different way, you have flexibility right upto to the SRAM balls.

Consequently, this from where your routing constraints should come from

1) The design guide of chip that drives the bus. How much skew does it have on outbound ? how much can it tolerate on inbound ? whats the delay between clk and addr ? how much skew is there btw dq/dqs ? how much skew on inbound dq/dqs can it tolerate ?
2) what is the spec from SDRAM vendor for correct operation ?

Based on spec in 1 & 2, you can come up with board delays that meet the system timing budgets, and translate it into routing length constraints...

i have a document see it i think it can helpful for u

its the same as you use a dimm, just the pin locations are different, they are not in a line, but at the chip sides. 4 chip: parallel 8 lines.
maybe the clk has to be buffered.
your BIOS has to know about your chip-timing, because you dont have an EEPROM filled with timing info, for the SPD.

Check the micron site...

check this attached doc.
I mention baseline for the DDR routing as per the signal group. similarly you can define for other signal group.

nikhil

see this