DDR SDRAM reference design

[davorin]

an223.pdf

Looked at DDR SDRAM manufacturer websites but didn't found any reference design connecting their components...

As datasheets are telling there must be some 1/2VDD termination applied?
To data signals only? And other signals connected as normal SDRAM via series resistor to controller?

 

[chinara]

I think this message may helpful for you. If you have any question please be free to contact me.

 

[davorin]

And which manufacturer supplies in lower quantities...or better said...which one does not only deliver to PC manufacturers?


Or one that even supplies samples for new development?

 

[cube007]

Hello,

Altera has got an Application Note for “Interfacing DDR SDRAM with Cyclone Devices”, also for other devices. Perhaps it is helpful.

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Bye,
cube007

 

[davorin]

Well..this is not my problem anymore as also I am not using Altera but Lattice EC/ECP devices (o;

 

[arcaphill]

Look it!

 

[cube007]

Interesting but very small seminar from EBV:

EBV_Design_and_Layout_Consideration_with_DDR_Memory.pdf