DDR-memory strobe to CLK routing rules

[buenos]

ddr length matching

hi

does anyone know whats are the rules (and why) for strobe to reference-clock trace length matching at DDR memories? i have an appnote for the CPU i am usung, there are concrete values, but no sufficient explanation.

i already have DDR appnotes, so please dont say things like that: "here is an appnote, there are lots of things about DDR..."

 

[layout guy]

ddr strobe

Hi,

I am a bit unclear what you are looking for. Can you be a bit more specific in your question?

Well, DDR signals are high-speed and they have to meet the specific speed requirements and that's why they have to be very closely matched and not to exceed the timing margins.

The matching rules depend on the DDR type and the memory arrangement as well as the controller interface type. The rules can differ, for an example if you are interfacing DDR to a specific memory controller in a daisy chain arrangemet vs. star topology.

Regardless of the topology you are using the DDR length matching groups are as follows:

ADDR and CTRL ( including ODT if used )
DATA and STROBE
CLOCKS

Hope this helps.

Layout Guy

 

[Rame]

ddr route star topology

Hi,

Search in this forum,you might get the answer for your query....


Regards

Ramesh

 

[buenos]

interfacing ddr memory.pdf

layout guy: thanx, but i alreay knew these. and the question was not so general, but more specific about data_strobe-to reference clock matching. this also exist.

ramesh: i couldnt find answer after searching the forum

 

[Rame]

ddr strobe

Hi,

Check this site out, look into 6th chapter,u might get some useful information.

**broken link removed**

Regards

Ramesh

 

[buenos]

ddr rules

thanx. it looks good.