Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

DDR memory interconnect

Status
Not open for further replies.

shaiko

Advanced Member level 5
Advanced Member level 5
Joined
Aug 20, 2011
Messages
2,644
Helped
303
Reputation
608
Reaction score
297
Trophy points
1,363
Activity points
18,302
Hello,

Leaving signal integrity issues aside - is it functionally possible to connect DDR3 memory to several masters over a single parallel bus?
 

Hi,

I don't think you can leave the signal integrity issues aside in DDR3, it would affect your circuit functionality.

Also, if these "several masters" you are talking about are processors, then no. As each processor think he is the master you would have collisions, and DDR3 is not prepared for this situation.

If your "several masters" are FPGAs, for example, you might try to implement some protocol to avoid collision, but it surely would cost logic (or better, latency inside FPGA) and slow down your DDR3 frequency. So, perhaps it might be possible, but I don't think it is wise.
 
  • Like
Reactions: shaiko

    shaiko

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top