Azrael
Newbie level 1
Hi everyone
When design a multi-voltage chip, the DDR goto a self-refresh state when the cke are low. But the major logic of the chip are power down, if the ddr controller and ddr phy are being power down, who will keep the cke down? Do they achieve this by outside pullup/down?
When design a multi-voltage chip, the DDR goto a self-refresh state when the cke are low. But the major logic of the chip are power down, if the ddr controller and ddr phy are being power down, who will keep the cke down? Do they achieve this by outside pullup/down?
