DCop Inconsistent

[ahmedokasha1999]

I'm designing a low voltage BGR circuit and for the last 4 days i was getting non realistic results from cadence.
In the first 2 pics. I'm perorming a temperature DC sweep and i'm getting results that is not expected.

But if i sweep the temperature backwards (125 to -40) i get the results i'm expecting.

I can live with that problem. But there's a bigger one. The DCop that cadence give me when i ran at a specific temperature is from the wrong graphs. And I need to run AC and Transient analysis at the nominal 27 temperature.

 

[Dominik Przyborowski]

Bipolar BGR?
Use node set or initial conditions for given temperature. Depending to architecture, you may force different nets, however at least do this for BJT terminals.

Short transient to dump operating point and reuse it in every other analysis should help as well.

 

[dick_freebird]

Probably either your startup circuit is missing, or
mis-calibrated.

Bandgaps without explicit startup will have -at least-
two stable DC solutions (there could be more, as the
feedback can flip from negative to positive at some
high current level, depending on device and circuit
details). But that's another problem for another time
as your issue seems to be between "off" and "closed
loop".

Many SPICEs leave a numerical "residue" which will
become the initial condition for the next iteration of
a loop (such as temperature sweeps). So if you have
a solution at -40C which shows "off", that "off" solution
is the first guess at (say) -20C solution, and if that
gets convergence, on to the next, and only a gross
numerical excursion or some change to device
characteristics (e.g. a strong roll-on of leakage or
subthreshold conduction) will break you out of that
"tradition".

Look to the startup circuit. A bandgap that pretends
to start without one, is just waiting to say "gotcha!"
at FOK wafer probe debug, or worse yet at low temp
final test with a PDA lot-reject limit.

 

[ahmedokasha1999]

Probably either your startup circuit is missing, or
mis-calibrated.

Bandgaps without explicit startup will have -at least-
two stable DC solutions (there could be more, as the
feedback can flip from negative to positive at some
high current level, depending on device and circuit
details). But that's another problem for another time
as your issue seems to be between "off" and "closed
loop".

Many SPICEs leave a numerical "residue" which will
become the initial condition for the next iteration of
a loop (such as temperature sweeps). So if you have
a solution at -40C which shows "off", that "off" solution
is the first guess at (say) -20C solution, and if that
gets convergence, on to the next, and only a gross
numerical excursion or some change to device
characteristics (e.g. a strong roll-on of leakage or
subthreshold conduction) will break you out of that
"tradition".

Look to the startup circuit. A bandgap that pretends
to start without one, is just waiting to say "gotcha!"
at FOK wafer probe debug, or worse yet at low temp
final test with a PDA lot-reject limit.

My circuit do have a startup circuit that I verified using DC sweep for the supply voltage and Ramping the supply in transient analysis.
But it seems to work only on some temperatures.
My guess it's something related to the simulator in low supply voltage. My supply spec is 0.99-1.1-1.21 V. But when i increase it to say 1.22 the whole circuit works just fine with or without the startup circuit.

 

[ahmedokasha1999]

Bipolar BGR?
Use node set or initial conditions for given temperature. Depending to architecture, you may force different nets, however at least do this for BJT terminals.

Short transient to dump operating point and reuse it in every other analysis should help as well.

Yes it's a bipolar BGR sorry for forgetting to mention that.
I did ao without any improvement.
I'm sorry for that, but could you explain how could I do that with some details?

 

[dick_freebird]

Well, classical bandgaps put out 1.2xx V so it
would be difficult to get a classical topology
to work below that, unless your PDK includes
a FLT (Free Lunch Transistor, that is). Maybe
there's a fold in there but between Vbe and
the necessary PTAT I*R, there's not a way to
get the "magic" output voltage in a straight
stack.

Bipolar bandgap is where I've seen the third
state (locked up at high current). Beware the
saturation behavior of your current mirrors
if you are using a simple PTAT 4-transistor
core.

 

[Dominik Przyborowski]

Well, classical bandgaps put out 1.2xx V so it
would be difficult to get a classical topology
to work below that, unless your PDK includes
a FLT (Free Lunch Transistor, that is). Maybe
there's a fold in there but between Vbe and
the necessary PTAT I*R, there's not a way to
get the "magic" output voltage in a straight
stack.

Don't worry, Banba and modified Brokaw can go below 1V.

My guess it's something related to the simulator in low supply voltage. My supply spec is 0.99-1.1-1.21 V. But when i increase it to say 1.22 the whole circuit works just fine with or without the startup circuit.

If working in transient it is ok, if not - circuit has issues to be solved.

I'm sorry for that, but could you explain how could I do that with some details?

You can force voltage at specific nodes for any analysis. In ADE doing it by RMB on test → Convergence Aids → Node Set or Initial Conditions (IC is stronger and used as a first point of transient, while NS is used as starting point to calculate DC OP).

More reliable is to use short transient and dump operating point to file and reuse in other analyses.
Set transient (has to be first on the analyses list) in which you starting circuit. In tran options provide filename for saving state.
In dc/ac options, provide the same filename in nodeset/initial condition option. Switch on force IC for nets.
In output log, you will get message that nodeset or initial conditions were loaded from given file.

For DC temp sweep, it might be also useful to tighten abstol, reltol, iabstol and vabstol parameters (by factor of 10).

In CDNS documentation (Virtuoso/ADE/Spectre) you can find more details.