Pharmboy
Newbie level 2
![Newbie level 2](/styles/images/ranks/alevel2.gif)
Hello, I couldn't find any information on this so I'm asking here.
When using a DCM / digital PLL to multiply up a clock does the rise/fall time of the clock limit the max frequency of the output clock in any way?
More specifically will the rise/fall of the output clock be identical to the input clock or will it be different? Say you use a PLL to double the input clock, will the rise/fall time be say.. cut in half or stay the same? If it stays the same, and both are at 4ns, wouldnt the max frequency you can pump out be f = 1/(2*4ns) = 125MHz otherwise the output clock will fail to reach the same high voltage level as the input clock?
Hope some of you guys know this, I know I could probly know this if I took the time to learn about the internal workings of DCM/PLL, but right know I dont have the time , I just need it as a 'black box'.
Thanks in advance for any reply..
When using a DCM / digital PLL to multiply up a clock does the rise/fall time of the clock limit the max frequency of the output clock in any way?
More specifically will the rise/fall of the output clock be identical to the input clock or will it be different? Say you use a PLL to double the input clock, will the rise/fall time be say.. cut in half or stay the same? If it stays the same, and both are at 4ns, wouldnt the max frequency you can pump out be f = 1/(2*4ns) = 125MHz otherwise the output clock will fail to reach the same high voltage level as the input clock?
Hope some of you guys know this, I know I could probly know this if I took the time to learn about the internal workings of DCM/PLL, but right know I dont have the time , I just need it as a 'black box'.
Thanks in advance for any reply..