ashrafsazid
Advanced Member level 4
Hi could anyone please tell me how to set a dc value for a clock in Veriloga module?
I have a clock generation code. The DC value is zero. If I want to change the initial_begin value to set the desired DC then the phase is reversed. Is there any other mean to set the dc value seperately?
I have a clock generation code. The DC value is zero. If I want to change the initial_begin value to set the desired DC then the phase is reversed. Is there any other mean to set the dc value seperately?
Code:
parameter real vdd = 1.8 ;
parameter real f_chop = 50k ;
parameter real tol = 1n ;
parameter real ClkDelay = 0 ;
parameter integer ChopEna = 1 ;
parameter integer offmode_Chop = 1 ;
@ (initial_step) begin
period = 1/f_chop;
tgl1 = 1;
end
@(timer(ClkDelay, 0.5*period)) begin
if (ChopEna>=1) begin
if(tgl1==1) begin
tgl1 = 0;
end else if(tgl1==0) begin
tgl1 = 1;
end
end else if (ChopEna==0) tgl1 = offmode_Chop;
V(ChopClk) <+ transition(vdd*tgl1, tol, tol, tol) ;
end