DC SDC: timing constraint at async spi slave

Hi,
I'm writing sdc file for DC to compile, and here's a case that I don't know how to deal with.
In my design, it has a spi slave module and an async fifo module. Spi slave is written in async which is the system clock oversamples spi_clk, spi_cs, spi_mosi, spi_miso. Meanwhile, the spi_clk is also used as the read clk of async fifo.
So I don't know how to constraint the spi_clk, should I treat it as a clock or a signal? And another question is about the delay value. I'm not sure if the set_input_delay value here is correctly given, its referencing the outside device's datasheet of spi mst timing, but maybe I should use the rule of 70/30 percent of the clock period to set, since the clk is main_clk. Part of my current constraint file are as shown below. Please give me some advises, thanks in advance.

# CREATE CLOCK
create_clock -name main_clk -period 3.6 [get_ports sys_clk]
create_clock -name spi_clk -period 37 [get_ports sck]

# SPI CONSTRAINT
set_input_delay -clock [get_clocks main_clk] -max 5 [get_ports CS]
set_input_delay -clock [get_clocks main_clk] -max 5 [get_ports MOSI]
set_input_delay -clock [get_clocks main_clk] -min -1.0 [get_ports MOSI]
set_output_delay -clock [get_clocks main_clk] -max 14 [get_ports MISO]
set_output_delay -clock [get_clocks main_clk] -min 2.5 [get_ports MISO]