[DC] how to solve a timing arc loop?

[Jordon]

Hi, i am synthezing some modules in Design Compiler, coming this problem. take a example ,a module called lut4ab,its timing is not good for me. I check the path, it has many mux_buf which is customized defined(the same thing happened in other modules),

It report breaking timng arc loops, but i think no combinational loop exists in RTL codes.

this is RTL codes

and i also check the GL codes

the unit define as below,

what should i do to slove the problem(synthesys timing is so bad and the timing loop) ?

 

[oratie]

Regarding timing loop warning: execute command check_timing AFTER the compile. If it say no timing loop - so no timing loop. Such warnings DURING comile may be a false warning (there is article in solvnet about these false warnings).

 

[Jordon]

Regarding timing loop warning: execute command check_timing AFTER the compile. If it say no timing loop - so no timing loop. Such warnings DURING comile may be a false warning (there is article in solvnet about these false warnings).

Thanks. I type check_timing after compile, but it still exists loop, is there some way to fix it(when RTL codes dont have combinational loop but compileOutcome have)?