We usually find ideal calculations in the land of unrealistic design assumptions where real world component parameters don't exist.Problem i am facing is that when MOSFET is on for 190us as per ideal calculation id should be ramp with ID(max)=8A.
Depending on the actual gate waveform, there may be switching losses that make IL drop before the current commutates to the secondary. An accurate measurement should be performed in the on-phase. I see that it needs a more sophisticated setup, but it's worth the effort.
Your current waveform shows, that the inductance is apparently larger than 300µH, as already assumed in post #3. To be sure, you'll want to check that the 12 V supply doesn't drop during on phase.
If you verified that the effect is not caused by a supply voltage drop, I would expect that the final dI/dt slope represents the real inductance. The higher initial di/dt may be caused by diode reverse recovery current or by the specific inductor characteristic.also note that current rises with higher rate initially but rise rate slowed down and continued for rest of time.
please tell what is stopping it to get peak current of 6.5A?
what kind of measurements can be used to identify the real problem of adding resistance in circuit? i am more intrested in finding the faults/limitations that are making my circuit to depart from ideal behavior before going to adopt some other design.
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