DC-DC , about gate drive circuit.

[rock_zhu]

Hi, all
There is a urgent question about the power pmos and nmos gate drive circuit.
The gate drive circuit is composed of invertor chain. PG and NG are the gate node of PMOS and NMOS respectively.
we know that for efficiency consieration this time interval should be in a range.
If the time is small there is short current and if the time is large the diode between drain ant source of NMOS will conduct current for a long time.

My question is how to set the interval time between the rising/falling edge of PG and NG? Is there any rule for this?
Thanks.
https://obrazki.elektroda.pl/24_1272426956.jpg

 

[amriths04]

It depends on your technology and can be found out only through simulations. Simulate across all corners and ensure that there is enough margin for the non-overlap time so that the supply does not short to ground or, the efficiency does not get hit.

 

[love_analog]

There are also some schemes that do adaptive control of this. I believe TI has something like this in their products. Google it.