[DC-Compiler] 'Characterize' command

Hello All,

Could anyone provide more details on the 'characterize' command of the DC-Compiler?

Actually the manual says the following: "characterize: captures information about the environment of specific cell instances and assigns the information as
attributes on the design to which the cells are linked. You can characterize manually or automatically." Could anyone provide more details?

When and why this command should be used?

Thank you!

Any help? Comments? When the command is needed? Thank you!

when you syntheiss your rtl code using bottom up you need to characterize sub modele when you sythesis top module. first you synthesis lower module save it then when you synthesis top module characterize the sub module.

Does the command characterize cells or modules?

As far as I understand, the flow is as following:
1) synthesize sub-modules
2) read their netlists to the Top Level
3) characterize sub-modules in the Top-Level in order to receive their timing information
4) compile/synthesize the Top-Level
Correct?

What will happen when using the same flow without characterization the sub-modules?

Thank you!

You are right and the reason for characterization is to provide top module's consstraint i.e. environment to lower sub module in order to synchronise the whole design. so first you syntheisis the lower submodule by giving them some constraint ans save it
2) read the sub module's netlist while you synthesis top module give constraint to top module and characterize the lower module in order to give them top module's environment. save those constraint
3) Again sytheisize the lower module's netlist with top module's constraint and save
4) read the submodule netlist again while you read top module's netlist and this time you make sure not to over write lower module's constraint by giving command set_dont_touch and compile the design.

one more you characterize instances which you use for sub module's in Top module.

if you not characterize the lower sub module means you are not making your design totally synchronous.

Thank you! Great answer! I've actually being looked for description of the flow for a long time!

one more you characterize instances which you use for sub module's in Top module

Click to expand...

is this a fifth step in the flow or just a commence for the first four steps?
Thank you