balamani
Member level 1
Hi
I am calculating the Data write time budget for DDR2 interface. I am using HyperLynx 8.2.1.
I referred the following document.
https://download.micron.com/pdf/technotes/ddr2/tn_47_01.pdf
Please refer the table 10 on page number 20.
I am trying to understand the procedure to calculate the INTERCONNECT skew.
1. How to calculate the following
a. Input capacitance matching
b. REFF mismatch
c. Input eye reduction (VREF)
2. On what basis, +/- 3.75% is considered for REFF mismatch? Is this value related to the tolerance of resistor divider used to generate Vref? 10 ps is mentioned against REFF mismatch. How do they arrive this value? What slew rate value is considered?
3. “±20mV included in DRAM skew; additional = (±25mV)/ (1.0 V/ns); this includes DQ and DQS” –comments against the Input eye reduction (VREF). How do they arrive at ±25mV ? Is the value 1.0 V/ns taken from simulation?
I am calculating the Data write time budget for DDR2 interface. I am using HyperLynx 8.2.1.
I referred the following document.
https://download.micron.com/pdf/technotes/ddr2/tn_47_01.pdf
Please refer the table 10 on page number 20.
I am trying to understand the procedure to calculate the INTERCONNECT skew.
1. How to calculate the following
a. Input capacitance matching
b. REFF mismatch
c. Input eye reduction (VREF)
2. On what basis, +/- 3.75% is considered for REFF mismatch? Is this value related to the tolerance of resistor divider used to generate Vref? 10 ps is mentioned against REFF mismatch. How do they arrive this value? What slew rate value is considered?
3. “±20mV included in DRAM skew; additional = (±25mV)/ (1.0 V/ns); this includes DQ and DQS” –comments against the Input eye reduction (VREF). How do they arrive at ±25mV ? Is the value 1.0 V/ns taken from simulation?