Data transfer to FPGA from computer through serial port.

[Sujatha_11]

open core fpga serial port

Hi,
I am doing a project using FPGA( a tester chip) and I am a graduate student. I am to transfer test vectors (1s and 0s) from a PC user interface to the FPGA RAM using serial port(computer's COM port). I leanrt how to configure the FPGA to send and receive data but not sure if I have to write some C code also along with VHDL code for this data transfer to happen. I am new to FPGA/VHDL. Can someone explain how exactly can we make this happen? what code has to be written where? Thanks. Urgent plz..

 

[Elnegm]

the signal reset_ibuf has no load.

I think in your FPGA you to implement UART module to deal with the COM port in PC if ypu will send data from FPGA to PC,but if the FPGA only reciecve data from PC ,so you will need small FSM on your FPGA to recieve UART frame and extract data from it and but it into RAM ,in both case you need to write c code on your PC in order to use COM port and send and recieve
And this site to interface with serial

and this is open source for UART module get it from open coures site

 

[Sujatha_11]

how to extrct data from fpga

Thanks a lot for your help.

 

[sixdegrees]

pc to fpga data transfer vhdl code

U may also look at this link its very good indeed...

**broken link removed**

sixdegrees

 

[Sujatha_11]

uart fpga computer

Sixdegrees,
You mean to say by using hyperterminal I don't have to write any C code for communication is it? And I have another problem. the input to the FPGA is going to bits as in I am designing a tester chip which takes in test vectors as inputs and expected reponses as inputs. So its just gonna be 1s and 0s. But when I use C or the hyperterminal the ascii equivalent of 1 or 0 would get transmitted right? Should I write a code to convert it to binary 1 and 0 is it a way to transfer it as binary digits itself? Please help me.

 

[sixdegrees]

fpga 到 cpu 的数据传输

Well if u had gone through the code which i had mentioned u will see that u dont have to write anything in C, its all Verilog and yes u can transfer bits as well. But just for curiosity what type of chip are u designing/testing, I am in testing too but do mostly theoretical stuff..

 

[Sujatha_11]

send data from pc to fpga

I am to do a tester chip in FPGA which is used to test other ICs so I need to transfer the test vectors and expected responses to the RAM in FPGA to be utilized for the DUT later. This is whr I need serial communication. BTW how do you transfer bits using Hyper Terminal? Plz let me know.

 

[mami_hacky]

provide inputs to fpga through pc

for FPGA side,

Use picoblaze UART module,

Very easy to use and flexible

for PC side on windows,
use WriteFile and CreateFile APIs
they should help to do the task

 

[sudarshan_onkar]

i have rs232 built into my board with max level converter and i have a cable which has D9 connector on both sides. Can i use this cable to connect my PC to FPGA ( Cable has provision to plug in on both cpu and fpga).

 

[onurdas]

Hi;
I am trying to send data to Spartan3 board via Hyperterminal. My aim is to display the ASCII code of character entered on leds. I designed a state machine but I can't get any output result. Any ideas?

/*
Initially it waits in IDLE ;
when receiver turns into 0 (start bit) it goes to BAUD state
for counting up to 5208,( for 9600 baud with 50MHz clock)
then WRITE state loads the current value of rxd to shift register.
These repeats until ctr reaches to 9,
all data and stop bit is obtained,
data is loaded to 'led' output and goes back to IDLE
*/


module ons(rxd, led, reset,clk);
input clk;
input rxd;
output [7:0] led;
input reset;

reg [1:0] state, next_state;
reg [8:0]sr;
reg [3:0]ctr;
reg [24:0] count;
reg [7:0] tmp;


parameter IDLE=2'b00, BAUD =2'b01, SREG=2'b10,WRITE=2'b11;

assign led = tmp;

always@(posedge clk or posedge reset)
begin
if(reset==1)
state <= IDLE;
else
state <= next_state;
end


always@(rxd or count or ctr or state)

begin
case(state)


IDLE:
if(rxd==0)
next_state <= BAUD;
else
next_state <=IDLE;


BAUD:

if(count== 25'b0000000000001010001010111)
next_state <= SREG;
else
next_state <= BAUD;

SREG:
if (ctr == 4'b1001)
next_state <= WRITE;
else
next_state <= BAUD;

WRITE:
next_state <=IDLE;
endcase
end


always@(posedge clk)

begin

case (state)

IDLE:
if (rxd==1)
begin tmp <= sr[8:1]; end

else if(rxd==0)
begin
sr <= 9'b000000000;
ctr <= 4'b0000;
end

BAUD:
begin

count <= count + 25'b0000000000000000000000001;

end

SREG:
begin
sr[8]<= rxd;
sr <= { sr[7:0], sr[8]};
ctr <= ctr + 4'b0001;
count <= 25'b0000000000000000000000000;//
end

WRITE:

begin tmp <= sr[8:1]; end

endcase

end

endmodule

 

[FvM]

Hello,

I didn't review your code in detail. One thing that should be corrected, if your code is according to the description you gave: When baud counter is restartet with RxD start bit, it must count 1,5bit times until sampling the first data bit, cause this should happen in the middle of bit interval. Usually, after 0,5 bit times, you should sample RxD for false start bit, optionally resetting the receiver.

One thing I can't get into my head: Does no Verilog textbook or HDL class ever mention other than binary constants? I'm not willing to check expressions as 25'b0000000000001010001010111 when you can write 25'd5207. The latter would be readable without using windows desktop calculator. Furthermore, it's obvious that the baud counter only needs 13 bits (unless you plan an option for 2 Hz baud rate). But that does no harm, the HDL compiler ignores unused resources anyway.

The basic structure and FSM usage seems correct at first look.

Regards,
Frank

 

[snowfall]

Check out the UART open core at the link here: **broken link removed**. You can adapt it to your application.

Cheers,
-s

 

[onurdas]

Thanks for the tip.
It keeps saying" The signal reset_IBUF has no load. PAR will not attempt to route this signal." Is this warning negligible?. The reset signal is already an input why should I load it?

 

[chimera086]

Re: the signal reset_ibuf has no load.

I think in your FPGA you to implement UART module to deal with the COM port in PC if ypu will send data from FPGA to PC,but if the FPGA only reciecve data from PC ,so you will need small FSM on your FPGA to recieve UART frame and extract data from it and but it into RAM ,in both case you need to write c code on your PC in order to use COM port and send and recieve
And this site to interface with serial

and this is open source for UART module get it from open coures site

Excuse me sir, im kinda confuse... you have posted the site to interface w/ serial but i still dont know how to implement things further... my question is, is there any exercise that i could follow step by step on implementing it... i dont know where to start...I have done so many research on the net but still i could not find one whom i could follow...all i want is to interface the spartan 3 to PC... what do i need? do i need to connect wire directly from PC to FPGA without any hardware schematics at the middle and then using hyperterminal in PC in sending data towards the FPGA but ofcourse the FPGA is program to receive data already... or is there a hardware for me to interface the PC to FPGA? if it is so, i dont know the schematic for this, i dont know how to do this thing... pls do help me sir... i really need your help for this... hope for your reply

 

[Jack// ani]

Re: the signal reset_ibuf has no load.

I think in your FPGA you to implement UART module to deal with the COM port in PC if ypu will send data from FPGA to PC,but if the FPGA only reciecve data from PC ,so you will need small FSM on your FPGA to recieve UART frame and extract data from it and but it into RAM ,in both case you need to write c code on your PC in order to use COM port and send and recieve
And this site to interface with serial

and this is open source for UART module get it from open coures site

Excuse me sir, im kinda confuse... you have posted the site to interface w/ serial but i still dont know how to implement things further... my question is, is there any exercise that i could follow step by step on implementing it... i dont know where to start...I have done so many research on the net but still i could not find one whom i could follow...all i want is to interface the spartan 3 to PC... what do i need? do i need to connect wire directly from PC to FPGA without any hardware schematics at the middle and then using hyperterminal in PC in sending data towards the FPGA but ofcourse the FPGA is program to receive data already... or is there a hardware for me to interface the PC to FPGA? if it is so, i dont know the schematic for this, i dont know how to do this thing... pls do help me sir... i really need your help for this... hope for your reply

This would be a good place to start:

http://www.fpga4fun.com/SerialInterface.html

Good luck

 

[muktoshuvro]

Choosing fpga device kit

hello there...
I found this site very helpful regrading FPGA. I need some suggestion about FPGA. Recently i have assigned a task where I have to program FPGA so that the usb port can send data in packet format. I need suggestion about which product(device kit) can be choosen for that. hope for the reply.....thnkssss