Hi HPC,
There are 2 methods you can do that:
1.Using traditional handshaking mechanism or
2.Using asynchronous FIFO memory
method 1 is not preferred when clock latency is the concern.
So if you have enough hardware resources, i recommend you to go for method 2.
Design of asyn FIFO is bit difficult if you are beginner but it's widely used for data transmission b/w diff clk domains.
You can refer attached documents for the design of such FIFO:
I would recommend to design sync FIFO(FIFO1.pdf) first and than move to asyn FIFO(FIFO2.pdf).