data shifting while DDR3 write with MIG

hi thank you very much

I have one very irritating results and for which I cannot sort out why, coz it is generated internal to MIG? So if you find some free time and can have a look at it I would be thankful for your suggestion over it

I am operating at clk_mem = 300 Mhz and clk = 150 Mhz and have data shifting while wiring. You can see the image in the figrure below whenre I have shown the difference between actual data and the shifting value. After some singnals this shifting increase more (but I have noticed it is only in multiples of 8).

Hence I would like you guys help in figuring out what is the problem here since I urgently have to submit the results for my thesis and this is the fundamental step. I don't udnerstand with checking all my logic and every thing what and where goes wrong...And if it is related to timing issue...I am doomed, doomed, doooomed....Just kidding but seriously have a look at it. please see the image below as well


I have tried to summarize it as:

1. In each case, signals on app_wdf_data were same as I expected but when I checked the wr_data_rise0, wr_data_fall0, wr_data_rise1, wr_data_fall1 in phy of MIG, I found that I get shifted signals there. I have tried to show in the image below

3. So can u know of any reason of this behaviour and data shift as I should say, it appears like in some inner buffer the data seems to store (like for example in FIFO, and it comes the new coming data. But why and how to trace down the problem.)

Thanks for your time.



Bests,
Shan