data latch for 200msecs

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sherakram

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hi,
i have a flag, say stop_flag.i want it to be latched for 200msec, i.e i want that flag to be active for 200msec. my clock is 10Mhz. any help regarding this is mostly gratifying.

thanks in advance
 

I would try it out in this way...
Using a counter and the 10MHz clk, generate a signal that is HIGH for 100ms and LOW for the next 100ms, that gives us 200ms. Use this signal as clk input to the stop_flag register.
 
NO. dont use generated signals as clocks (its bad design practice in FPGAs)
Use a counter as dpaul suggest, but make it high for 1 clock cycle every 100ms. Then use this as a clock enable on the stop_flag register.
 
dpaul said:
I would try it out in this way...
Using a counter and the 10MHz clk, generate a signal that is HIGH for 100ms and LOW for the next 100ms, that gives us 200ms. Use this signal as clk input to the stop_flag register.
Click to expand...

hi dpaul,
Thank you for your help, actually my requirement is, i will get a pulse (of 0.1usec) only once , i need to generate a logic high signal after 200msec of this 0.1usec pulse is occurred. i.e I want to generate a delay of 200msec after that pulse is occurred. So my design should start with that pulse and after 200msecs it should stop by setting a flag high.
 


You want a pulse stretcher...

synchronizer (if required)
edge detector
synchronous set/reset flip-flop, the out_pulse (set on edge detector, clear on terminal count value)
counter (clear when out_pulse is 0, count when out_pulse is 1)

That should do the trick, though if you need to extend the pulse if another input pulse occurs or if you need to "save" input pulses and produce the same number of output pulses, those implementations are left as an exercise for the reader.
 


thank you ads-ee, it worked.
 

data latching on every rising edge of clk

hi.........,
i need a design in which a signal should be in logic high state at rising edge of clk and it should retain that state for 100ns then shift to logic low state n should retain that logic low state till next rising edge occurred. any help regarding this is mostly apreciable.

thanks in advance.
 

Re: data latching on every rising edge of clk

In synchronous logic every action is scheduled by clock edges, e.g. timing a signal for 100 ns. Means you'll want a sufficient fast clock. There's no other way to generate a delay.

- - - Updated - - -

P.S.: I noticed that you already started a similar thread. The answers given therein apply more or less for the 100 ns pulse width.
 

Hi,
I'm doing such things by creating state machine with states
Waiting, Delay,
condition Waiting => Delay is any sort of triggering event you have,
While in delay set flag to '1'. while in Waiting set flag to '0'
condition Delay => Waiting is counter value equals to number of ticks you want to wait.
Counter is incrementing every tick when state machine is in Delay state, reset on transition Waiting => Delay

If you need help, let me know, I will send you code for that.

Cheers,
XBD
 

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