Data converter terminology

Hey guys,

When you look at some papers or datasheets for ADCs, they use the term MSPS, like 10-bit 500 MSPS. I don't exactly know how we can interpret MSPS. Does it mean this ADC can generate 500 mega sample per second at output of the ADC, and each sample has 10 bits, or it is related to the input signal, or ....
Besides, can we get any information if we do not know how many cycles it may take each input signal to be converted to the digital word.

thanks!

MSPS is mega-samples per second. The easiest way to think about this is if you have it continuously generating output codes, you'll get 500MS/s, where each output code is N bits (N being the resolution of the ADC).

As for the number of cycles, that completely depends on the type of ADC. For example, a SAR ADC takes N cycles or so, where N is the number of bits, but it's N cycles of a clock that may be internally generated or asynchronous to your system. The ADC datasheets should have a description of the necessary input clock(s) and start signals.

I hope that helps!

jsherman said:

MSPS is mega-samples per second. The easiest way to think about this is if you have it continuously generating output codes, you'll get 500MS/s, where each output code is N bits (N being the resolution of the ADC).

As for the number of cycles, that completely depends on the type of ADC. For example, a SAR ADC takes N cycles or so, where N is the number of bits, but it's N cycles of a clock that may be internally generated or asynchronous to your system. The ADC datasheets should have a description of the necessary input clock(s) and start signals.

I hope that helps!

Click to expand...

Thanks for your response. So you mean if an ADC spec is 10-bit 500MSPS, it means this converter generates 500*1e6*(10) bits per second, or 500*1e6 digital word/s, and based on what you said, if they report any spec like what I mentioned, all those internal clock stuff has been considered before and we don't need to conside them again. And also to me we can replace MSPS with Hz and say 500MSPS ADC has 500MHz input clock since it samples the input signal with that speed, am I correct?

Yes, if the ADC spec is 10-bit 500MSPS, it will generate 500*1e6 10 bit words per second.

As for replacing MSPS with Hz, that's a little different. Let's take a look at an example 10 bit, 500MS/s ADC on digikey:
https://www.intersil.com/content/dam/Intersil/documents/fn76/fn7606.pdf
Scroll down to page 8 and you'll see two timing diagrams. Each one has a time "t_{pd}" from the clock rise to the output of data. That will determine your maximum clock frequency input. In this case, it ranges from 1.74ns to 3.83ns. Based on this, I find it hard to believe that you can get a reliable 500MS/s (unless I'm reading the datasheet incorrectly, which is entirely possible). The datasheet also states that you need a differential clock signal for best performance, so you'll need an inverter on this guy as well.
In short, yes, you should be able to feed a 500MS/s ADC with a 500MHz clock, but you should always check the datasheet!